DETAILED ACTION
Status of Claims
Claims 21 – 40 are pending.
Claims 1-20 have been cancelled.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21, 27, 28, 30, 35, 36 and 39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 11, and 14 of U.S. Patent No. 12,197,268. Although the claims at issue are not identical, they are not patentably distinct from each other because they are directed toward the same invention; a system, including a plurality of component circuits, wherein the plurality of component circuits may include rate control circuits that control power consumption in the component circuits based on indications of power allocated to the component circuits. The rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation. Similarities of the claim limitation are provided in the table below (emphasis added by the Examiner).
Instant Application No. ‘831
Patent No. ‘268
21. A multi-die system, comprising: a plurality of systems on a chip (SoCs) coupled via a die-to-die interconnect, wherein a respective one of the SoCs includes: a plurality of component circuits configured to consume power from a voltage regulator shared by the SoCs; and a power splitter circuit configured to: allocate power to the plurality of component circuits based on a power budget for the respective SoC; determine, based on a current power allocation to the plurality of component circuits, that an unallocated portion of the power budget remains available; and transmit an indication of the unallocated portion of the remaining power budget to a corresponding power splitter circuit in another one of the SoCs over the die-to-die interconnect.
27. The multi-die system of claim 26, wherein: the respective rate control circuits are configured to generate respective power requests and respective floor requests for the power splitter circuit, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits; and the power splitter circuit is configured to ensure that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests; and the power splitter circuit is configured to allocate remaining power budget based on a power split policy and the respective power requests.
28. The multi-die system of claim 21, wherein, to allocate the power, the power splitter circuit is configured to: implement a power split policy, wherein the power split policy includes: a first level policy that specifies a split of the power budget among respective types of component circuits; and a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type.
1. A system comprising: a plurality of component circuits, wherein respective component circuits of the plurality of component circuits comprise respective rate control circuits; and a power splitter circuit coupled to the plurality of component circuits, wherein: the power splitter circuit is configured to allocate power to the plurality of component circuits based on a power budget for the system; the respective rate control circuits are configured to generate respective power requests and respective floor requests for the power splitter circuit, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits; the power splitter circuit is configured to ensure that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests; and the power splitter circuit is configured to allocate remaining power budget based on a power split policy and the respective power requests, wherein the power split policy includes: a first level policy that specifies a split of the remaining power budget among respective types of component circuits; and a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type.
30. A method, comprising: allocating, by a first power splitter circuit of a first system on a chip (SoC) included in a multiple-die system, power to a plurality of component circuits in the first SoC based on a power budget for the first SoC, wherein the first SoC shares a voltage regulator with a second SoC included in a multiple-die system; determining, by the first power splitter circuit and based on a current power allocation to the plurality of component circuits, that an unallocated portion of the power budget remains available; and transmitting, by the first power splitter circuit and via a die-to-die interconnect between the first and second SoCs, an indication of the unallocated portion of the remaining power budget to a second power splitter circuit in the second SoC.
35. The method of claim 31, wherein the allocating includes: receiving, by the first power splitter circuit, respective floor requests and respective power requests associated with the plurality of component circuits; ensuring, by the first power splitter circuit, that the plurality of component circuits receive an allocation of power at least equal to a minimum of respective floor requests and respective power requests; and allocating, by the first power splitter circuit, remaining power budget based on a power split policy and the respective power requests.
14. A method comprising: generating respective power requests and respective floor requests for a power splitter circuit in a system by respective rate control circuits in respective component circuits of a plurality of component circuits in the system, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits; and allocating power to the plurality of component circuits by the power splitter circuit, wherein the allocating comprises: ensuring that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests; and allocating remaining power budget based on a power split policy and the respective power requests, wherein the power split policy includes: a first level policy that specifies a split of the remaining power budget among respective types of component circuits; and a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type.
36. A computing system, comprising: a plurality of systems on a chip (SoCs);a first voltage regulator shared by first and second ones of the plurality of SoCs; and a die-to-die interconnect coupling together the plurality of SoCs; wherein the first SoC includes: a first power splitter circuit configured to: allocate power to component circuits of the first SoC based on a first power budget of the first voltage regulator; determine, based on a current power allocation to the component circuits, that an unallocated portion of the first power budget remains available; and send, over the die-to-die interconnect, an indication of the unallocated portion of the remaining power budget to cause a second power splitter circuit in the second SoC to allocate power to component circuits of the second SoC.
39. The computing system of claim 36, wherein, to allocate the power, the first power splitter circuit is configured to: implement a power split policy, wherein the power split policy specifies a split of the first power budget among respective types of component circuits and specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type.
11. A system comprising: a plurality of integrated circuits implemented on respective semiconductor substrates, wherein the plurality of integrated circuits are coupled via an inter-chip interconnect, wherein a respective integrated circuit of the plurality of integrated circuits comprises: a plurality of component circuits, wherein respective component circuits of the plurality of component circuits comprise respective rate control circuits; and a power splitter circuit coupled to the plurality of component circuits, wherein: the power splitter circuit is configured to allocate power to the plurality of component circuits based on a power budget for the respective integrated circuit; the respective rate control circuits are configured to generate respective power requests and respective floor requests, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits; the power splitter circuit is configured to ensure that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests; the power splitter circuit is configured to allocate remaining power budget based on a power split policy and the respective power requests, wherein the power split policy includes: a first level policy that specifies a split of the remaining power budget among respective types of component circuits; and a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type; and the power splitter circuit is configured to transmit an indication of an unallocated portion of the remaining power budget to the power splitter circuit in another integrated circuit of the plurality of integrated circuits over the inter-chip interconnect.
Appropriate action is required.
Allowable Subject Matter
Claims 22-26, 29, 31-34, 37, 38, and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu; Chia-Lin et al. (US Patent Application Publication No. 2016/0054776 A1) “Method For Performing System Power Control Within An Electronic Device, And Associated Apparatus” is cited to teach a method for performing system power control within an electronic device and an associated apparatus. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index.
Piszczek; Michael J et al. (US Patent No. 9477279) “Data Storage System With Active Power Management And Method For Monitoring And Dynamical Control Of Power Sharing Between Devices In Data Storage System” is cited to teach a data storage system with an active power monitoring and control performed by a control node elected among a number of nodes. A real-time power monitoring information is supplied to the control node from, a power monitoring logic residing at each device in the system. The devices in the data storage system are pre-allocated with respective individual power budgets which are below the maximum power usage thereof. The power budgets of all the equipment cumulatively constitute a power budget assigned to the group of equipment. The control node controls dynamically and in real time power sharing between the plurality devices so that the devices with required power usage below the pre-allocated power budget can share their extra power credits with devices which are in need for extra power for performing its operation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
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