DETAILED ACTION
This action is in response to the filing 04/13/2026. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are rejected under a nonstatutory double patenting rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-6, 8-12 and 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-7, 10-13, 16, and 18 of U.S. Patent No. 11907570. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim language of the instant application is anticipated by or broader than the claim language of the copending application. An analysis of Claims 1-6, 8-12, and 15-19 is provided below:
INSTANT APPLICATION
U.S. PATENT No. 11907570
[CLAIM 1] A method, comprising: performing a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determining that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and performing a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 1] A method, comprising: ... performing a test read operation on the first block prior to performing a read operation on the first block;
determining, at the memory sub-system and based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die of the memory sub-system,
wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block;
and performing a write operation to write the data from the first block of the first memory die to a second block of the first memory die based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 2] The method of claim 1, wherein the first degradation threshold is associated with data recovery of the first memory die.
[CLAIM 1] wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block
[CLAIM 3] The method of claim 1, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 6] wherein the first degradation threshold is based at least in part on a configuration of the first memory die or the memory sub-system.
[CLAIM 4] The method of claim 1, further comprising: determining the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 4] determining the number of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the number of read operations.
[CLAIM 5] The method of claim 1, further comprising: performing a second read operation on a second block based at least in part on performing the write operation to write data from the first block of the first memory die to the second block of the first memory die; detecting an error in the second block based at least in part on performing the second read operation on the second block; and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 5] performing a read operation on the second block based at least in part on performing the write operation to write the data from the first block of the first memory die to the second block of the first memory die; detecting an error in the second block based at least in part on performing the read operation on the second block; and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error
[CLAIM 6] The method of claim 1, further comprising: monitoring the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring.
[CLAIM 1] monitoring, at the memory sub-system, a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determining, at the memory sub-system and based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold
[CLAIM 8] A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 7] A system comprising: a plurality of memory components; and a processing device, operatively coupled with the plurality of memory components, to: ... perform a test read operation on the first block prior to performing a read operation on the first block [Examiner note: the processing device being operatively coupled to the plurality of memory components inherently comprises "circuitry"]
detect, at the memory sub-system and based at least in part on performing the read operation, that a bit error rate degradation for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die
wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block
and write the data from the first block of the first memory die to a second block of the first memory die based at least in part on detecting that the bit error rate degradation satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 9] The memory system of claim 8, wherein the first degradation threshold is associated with data recovery of the first memory die.
[CLAIM 7] the first degradation threshold associated with data recovery for the first memory die
[CLAIM 10] The memory system of claim 8, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 12] wherein the first degradation threshold is based at least in part on a configuration of the first memory die
[CLAIM 11] The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 10] determine the number of read operations that triggers the data recovery procedure for the first block, the processing device to write the data based at least in part on the number of read operations.
[CLAIM 12] The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: perform a second read operation on a second block based at least in part on performing the write operation to write data from the first block of the first memory die to the second block of the first memory die; detect an error in the second block based at least in part on performing the second read operation on the second block; and perform a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 11] perform a read operation on the second block based at least in part on writing the data from the first block of the first memory die to the second block of the first memory die; detecting an error in the second block based at least in part on performing the read operation on the second block; and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 15] A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 13] A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: ... perform a test read operation on the first block prior to performing a read operation on the first block;
determine, at the memory sub-system and based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die
wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block
and perform a write operation to write the data from the first block of the first memory die to a second block of the first memory die based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 16] The non-transitory computer-readable medium of claim 15, wherein the first degradation threshold is associated with data recovery of the first memory die.
[CLAIM 13] wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block
[CLAIM 17] The non-transitory computer-readable medium of claim 15, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 18] wherein the first degradation threshold is based at least in part on a configuration of the first memory die
[CLAIM 18] The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to: determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 16] determine the number of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the number of read operations.
[CLAIM 19] The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to: monitor the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring.
[CLAIM 13] monitor, at the memory sub-system, a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determine, at the memory sub-system and based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die
Claims 1-15 and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-8, 11-15, 18, and 20 of U.S. Patent No. 12175133. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim language of the instant application is anticipated by or broader than the claim language of the copending application. An analysis of Claims 1-15 and 17-19 is provided below:
INSTANT APPLICATION
U.S. PATENT No. 12175133
[CLAIM 1] A method, comprising: performing a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determining that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and performing a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 1]A method, comprising: performing a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determining, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and performing a write operation to write data from the first block of the first memory die to a second block of the first memory die based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 2] The method of claim 1, wherein the first degradation threshold is associated with data recovery of the first memory die.
[CLAIM 7] wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth
[CLAIM 3] The method of claim 1, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 6] wherein the first degradation threshold is based at least in part on a configuration of the first memory die.
[CLAIM 4] The method of claim 1, further comprising: determining the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 4] determining the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 5] The method of claim 1, further comprising: performing a second read operation on a second block based at least in part on performing the write operation to write data from the first block of the first memory die to the second block of the first memory die; detecting an error in the second block based at least in part on performing the second read operation on the second block; and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 5] performing a second read operation on the second block based at least in part on performing the write operation to write the data from the first block of the first memory die to the second block of the first memory die; detecting an error in the second block based at least in part on performing the second read operation on the second block; and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 6] The method of claim 1, further comprising: monitoring the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring.
[CLAIM 1] monitoring a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determining, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold
[CLAIM 7] The method of claim 1, wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof.
[CLAIM 7] wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof.
[CLAIM 8] A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 8] A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation to write data from the first block of the first memory die to a second block of the first memory die based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 9] The memory system of claim 8, wherein the first degradation threshold is associated with data recovery of the first memory die.
[CLAIM 14] wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth
[CLAIM 10] The memory system of claim 8, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 13] wherein the first degradation threshold is based at least in part on a configuration of the first memory die.
[CLAIM 11] The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 11] determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 12] The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: perform a second read operation on a second block based at least in part on performing the write operation to write data from the first block of the first memory die to the second block of the first memory die; detect an error in the second block based at least in part on performing the second read operation on the second block; and perform a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 12] perform a second read operation on the second block based at least in part on performing the write operation to write the data from the first block of the first memory die to the second block of the first memory die; detect an error in the second block based at least in part on performing the second read operation on the second block; and perform a recovery procedure to retrieve the data of the second block based at least in part on detecting the error.
[CLAIM 13] The memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to: monitor the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring.
[CLAIM 8] monitor a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determine, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold
[CLAIM 14] The memory system of claim 8, wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof.
[CLAIM 14] wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof.
[CLAIM 15] A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 15] A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to: perform a test read operation on a first block of a first memory die prior to performing a read operation on the first block;
determine, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die;
herein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure;
and perform a write operation to write data from the first block of the first memory die to a second block of the first memory die based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation.
[CLAIM 17] The non-transitory computer-readable medium of claim 15, wherein the first degradation threshold is associated with a configuration of the first memory die.
[CLAIM 20] wherein the first degradation threshold is based at least in part on a configuration of the first memory die.
[CLAIM 18] The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to: determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 18] determine the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations.
[CLAIM 19] The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processing circuitry of the electronic device, cause the electronic device to: monitor the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring.
[CLAIM 15] monitor a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determine, based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11907570.
Regarding Claim 13, U.S. Patent No. 11907570 recites,
monitor the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring (“monitoring, at the memory sub-system, a bit error rate for the first block of the first memory die based at least in part on performing the read operation; determining, at the memory sub-system and based at least in part on the monitoring, that a degradation of the bit error rate for the first block of the first memory die satisfies a first degradation threshold” [Claim 1])
However, U.S. Patent No. 11907570 Claim 1 does not recite the method of Claim 1 being performed on a memory system. It would have been obvious to one of ordinary skill in the art to implement the method of Claim 1 of Patent No. 11907570 a memory system as recited by instant Claim 13. The resulting combination allows for the method acting upon the device to be practically executed.
Claims 16 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12175133.
Regarding Claim 16, U.S. Patent No. 12175133 recites,
wherein the first degradation threshold is associated with data recovery of the first memory die (“wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth” [Claim 7])
However, U.S. Patent No. 12175133 Claim 7 does not recite the method of Claim 7 being performed on a non-transitory computer-readable medium. It would have been obvious to one of ordinary skill in the art to implement the method of Claim 1 of Patent No. 12175133 on non-transitory computer readable medium as recited in instant Claim 16. The resulting combination allows for the method acting upon the device to be practically executed.
Regarding Claim 20, U.S. Patent No. 12175133 recites,
wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof. (“wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, the bit error rate, or any combination thereof” [Claim 7])
However, U.S. Patent No. 12175133 Claim 7 does not recite the method of Claim 7 being performed on a non-transitory computer-readable medium. It would have been obvious to one of ordinary skill in the art to implement the method of Claim 1 of Patent No. 12175133 on non-transitory computer readable medium as recited in instant Claim 20. The resulting combination allows for the method acting upon the device to be practically executed
Response to Arguments
Applicant’s arguments filed 04/13/2026 have been fully considered and are persuasive. Accordingly, the previous rejection under 35 U.S.C. 103 has been withdrawn.
In the interest of compact prosecution, the examiner attempted to contact the attorney at the number provided on Pg. 9 of the remarks on 6/22/26 and 6/23/26 because this application would have been in condition for allowance pending filing of the appropriate terminal disclaimers, however no response was received.
Conclusion
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/A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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