DETAILED ACTION
This action is in response to the application filed 11/27/2024. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-9, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Singidi (U.S. PGPub No. 20190065331) in view of Kumar (C.N. Patent No. 109427406).
Regarding Claim 1, Singidi teaches,
A method, comprising: performing a test read operation on a first block of a first memory die prior to performing a read operation on the first block (where the process described also in [0062] (see below rejection) may be performed in response to a request read command from a host [0110]);
determining that a degradation of a bit error rate for the first block of the first memory die satisfies a first degradation threshold (a first memory block is read and compared to a first error threshold [0062]; see [0031] for bit error)
a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die (where different types of memory cells may include different bit error rates [0037]),
and performing a write operation based at least in part on determining that the bit error rate satisfies the first degradation threshold or on an unsuccessful test read operation (where when the error rate exceeds the first threshold, data from the first block is written to a second block ("write operation") [0064]).
Singidi does not appear to disclose and Kumar teaches,
wherein the first degradation threshold is set according to a quantity of read operations that triggers a data recovery procedure (where a quantity of read operations triggers read check testing [pg. 31; n0069]);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory scrubbing operation as disclosed by Singidi to include performing read scrubbing after a particular quantity of read operations as disclosed by Kumar. The resulting combination allows for blocks to be read-checked more or less frequently according to pre-existing number of bit errors [Kumar; pg. 31; n0069], which allows for higher-error blocks to be addressed more frequently and therefore increase reliability.
Regarding Claim 2, Singidi does not appear to disclose and Kumar teaches,
wherein the first degradation threshold is associated with data recovery of the first memory die (where the error threshold may be set according to the system's error correction capability percentage [pg. 7; n0013]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory scrubbing operation as disclosed by Singidi to include a dynamic first threshold according to the data recovery of the memory die as taught by Kumar. The resulting combination allows for die with worse data recovery (higher bit errors) to be read-checked more frequently to increase problematic-die reliability.
Regarding Claim 4, Singidi does not appear to disclose and Kumar teaches,
determining the quantity of read operations that triggers the data recovery procedure for the first block, wherein the write operation is performed based at least in part on the quantity of read operations (where a quantity of read operations triggers read check testing [pg. 31; n0069]).
The same motivation for Claim 1 also applies to Claim 4.
Regarding Claim 5, Singidi teaches,
performing a second read operation on a second block based at least in part on performing the write operation to write data from the first block of the first memory die to the second block of the first memory die (when data is written to a memory (examiner note: i.e., following the error threshold writing to the second memory block [0064], the memory controller may read the written-to memory blocks to determine read error counts [0062]);
detecting an error in the second block based at least in part on performing the second read operation on the second block (where the written-to (second block) is read to determine read counts ("detecting an error") [0062]);
and performing a recovery procedure to retrieve the data of the second block based at least in part on detecting the error (where when the detected error(s) are found, the system may erase and rewrite those memory blocks ("recovery procedure") [0062]).
Regarding Claim 6, Singidi teaches,
The method of claim 1, further comprising: monitoring the bit error rate associated with the first block of the first memory die, wherein determining that the degradation of the bit error rate satisfies the first degradation threshold is based at least in part on the monitoring (the system may comprise a management table configured to maintain various information associated with component(s) of the memory device, including bit error counts (examiner note: therefore performing monitoring) [0031]).
Regarding Claim 7, Singidi teaches [in bold],
wherein the first degradation threshold is based at least in part on a [data recovery rate, a data recovery depth], the bit error rate, or any combination thereof (where the first threshold is according to bit error counts [0031+0062]).
Singidi does not appear to disclose and Kumar teaches,
wherein the first degradation threshold is based at least in part on a data recovery rate, a data recovery depth, … (where the error threshold may be set according to the system's error correction capability percentage [pg. 7; n0013])\
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory scrubbing operation as disclosed by Singidi to include a dynamic first threshold according to the data recovery of the memory die as taught by Kumar. The resulting combination allows for die with worse data recovery (higher bit errors) to be read-checked more frequently to increase problematic die reliability.
Claims 8-9 and 11-14 recite a shift in statutory category and are rejected under 35 U.S.C. 103 by Singidi in view of Kumar for the same reasons as Claims 1-2 and 4-7, respectively, above.
Claims 15-16 and 18-20 recite a shift in statutory category and are rejected under 35 U.S.C. 103 by Singidi in view of Kumar for the same reasons as Claims 1-2, 4, and 6-7, respectively, above.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Singidi in view of Kumar, further in view of Yang et al. (U.S. PGPub No. 20210263821).
Regarding Claim 3, Singidi does not appear to disclose and Kumar teaches that the error threshold may be based on the read threshold [pg. 7-8; n0015] but fails to explicitly disclose, while Yang teaches,
wherein the first degradation threshold is associated with a configuration of the first memory die (where read thresholds are stored as a configuration parameter per cell [0139]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory scrubbing operation as disclosed by Singidi in view of Kumar to include memory scrubbing bit error thresholds being associated with die configuration as taught by Yang. The resulting combination allows for the configuration parameter of read thresholds [Yang; 0139] to be proactively set and adjusted before an error occurs, allowing for prevention of certain errors without performance penalty [Yang; 0138].
Claim 10 recites a shift in statutory category and is rejected under 35 U.S.C. 103 as being unpatentable over Singidi in view of Kumar, further in view of Yang, for the same reasons as Claim 3, above.
Claim 17 recites a shift in statutory category and is rejected under 35 U.S.C. 103 as being unpatentable over Singidi in view of Kumar, further in view of Yang, for the same reasons as Claim 3, above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Reusswig et al. (U.S. PGPub No. 20180053562) discloses a technology for detecting read disturb in memory blocks subjected to a minimum number of read operations by comparing a number of errors to a limit.
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/A.E.W./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113