DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,164,437. Although the claims at issue are not identical, they are not patentably distinct from each other because the independent claims are nearly identical and cover the same material while the dependent claims of the instant application merely specify certain things that are still covered under the protection of the patent.
Instant Application
Patent 12,164,437
1. An apparatus, comprising: a volatile memory device comprising a first array of volatile memory cells; a non-volatile memory device comprising a second array of non-volatile memory cells; and a controller coupled with the volatile memory device and the non-volatile memory device, and configured to cause the apparatus to: generate a first physical address of the first array of volatile memory cells based at least in part on a read command indicating a logical address of the first array of volatile memory cells; read, based at least in part on the first physical address, a location identifier from a second physical address of the second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells; and verify that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
7. The apparatus of claim 1, further comprising: an access circuit coupled with the controller and the first array of volatile memory cells, the access circuit configured to perform one or more access operations associated with the first array of volatile memory cells, wherein the controller is further configured to operate the access circuit and the first array of volatile memory cells at one or more different voltages than the second array of non-volatile memory cells.
8. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to: operate the first array of volatile memory cells and the access circuit at a higher voltage than the second array of non-volatile memory cells.
1. An apparatus, comprising: a volatile memory device comprising a first array of volatile memory cells; a non-volatile memory device comprising a second array of non-volatile memory cells; and a controller coupled with the volatile memory device and the non-volatile memory device and configured to cause the apparatus to: generate a first physical address of the first array of volatile memory cells based at least in part on decoding a logical address of the first array of volatile memory cells indicated by a read command; read a location identifier from a second physical address of the second array of non-volatile memory cells based at least in part on generating the first physical address, wherein the second physical address of the second array of non-volatile memory cells is the same as the first physical address of the first array of volatile memory cells; determine, based at least in part on reading the location identifier, whether the location identifier corresponds to the logical address; and verify that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: read a data word from the first physical address of the first array of volatile memory cells based at least in part on generation of the first physical address, wherein, to read the location identifier, the controller is configured to cause the apparatus to read a location indicia from the second physical address of the second array of non-volatile memory cells, wherein verifying that the first physical address was generated without one or more errors is based at least in part on reading the data word from the first array of volatile memory cells and determining that the location indicia corresponds to the logical address.
3. The apparatus of claim 2, wherein: the location indicia is read before reading the data word, or the location indicia is read after reading the data word.
4. The apparatus of claim 2, wherein the location indicia is read concurrently with reading the data word.
5. The apparatus of claim 2, wherein, to determine that the location indicia corresponds to the logical address, the controller is configured to cause the apparatus to: determine that the location indicia corresponds to the logical address based at least in part on determining that the location indicia corresponds to the second physical address.
6. The apparatus of claim 2, wherein the location indicia comprises: the first physical address, a column of the first physical address, a row of the first physical address, a hash of the first physical address, or any combination thereof; or the logical address, a column of the logical address, a row of the logical address, a hash of the logical
3. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: read data associated with the read command from the first physical address based at least in part on generating the first physical address.
8. The apparatus of claim 1, wherein the location identifier comprises the logical address or a hash of the logical address.
9. An apparatus, comprising: a volatile memory device comprising a first array of volatile memory cells; a non-volatile memory device comprising a second array of non-volatile memory cells; and a controller coupled with the volatile memory device and the non-volatile memory device, and configured to cause the apparatus to: generate a first physical address of the first array of volatile memory cells based at least in part on a write command indicating a logical address of the first array of volatile memory cells; read, based at least in part on the first physical address, a location identifier from a second physical address of the second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells; and verify that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
13. The apparatus of claim 9, further comprising: an access circuit coupled with the controller and the first array of volatile memory cells, the access circuit configured to perform one or more access operations associated with the first array of volatile memory cells, wherein the controller is further configured to operate the access circuit and the first array of volatile memory cells at one or more different voltages than the second array of non-volatile memory cells.
14. The apparatus of claim 13, wherein the controller is further configured to cause the apparatus to: operate the first array of volatile memory cells and the access circuit at a higher voltage than the second array of non-volatile memory cells.
9. An apparatus, comprising: a volatile memory device comprising an array of volatile memory cells; a first non-volatile memory device comprising a first array of non-volatile memory cells; a second non-volatile memory device comprising a second array of non-volatile memory cells; and a controller coupled with the volatile memory device, the first non-volatile memory device, and the second non-volatile memory device and configured to cause the apparatus to: generate a first physical address of the array of volatile memory cells based at least in part on decoding a logical address of the array of volatile memory cells indicated by a read command, read a first location identifier from a second physical address of the first array of non-volatile memory cells based at least in part on generating the first physical address, the second physical address corresponding to the first physical address; read a second location identifier from a third physical address of the second array of non-volatile memory cells based at least in part on generating the first physical address, the third physical address corresponding to the first physical address; determine, based at least in part on reading the first location identifier and the second location identifier, whether the first location identifier and the second location identifier correspond to the logical address; and verify that the first physical address was generated without one or more errors based at least in part on determining that the first location identifier and the second location identifier correspond to the logical address.
10. The apparatus of claim 9, wherein the controller is further configured to cause the apparatus to: read a location indicia from the second physical address of the second array of non-volatile memory cells, wherein verifying that the first physical address was generated without one or more errors is based at least in part on determining that the location indicia corresponds to the logical address.
11. The apparatus of claim 10, wherein, to determine that the location indicia corresponds to the logical address, the controller is configured to cause the apparatus to: determine that the location indicia corresponds to the logical address based at least in part on determining that the location indicia corresponds to the second physical address.
11. The apparatus of claim 9, wherein the controller is further co figured to cause the apparatus to: read data associated with the read command from the first physical address based at least in part on generating the first physical address.
12. The apparatus of claim 10, wherein the location indicia comprises: the first physical address, a column of the first physical address, a row of the first physical address, a hash of the first physical address, or any combination thereof; or the logical address, a column of the logical address, a row of the logical address, a hash of the logical address, or any combination thereof.
17. The apparatus of claim 10, wherein the first location identifier comprises a first hash of at least a portion of the logical address and the second location identifier comprises a second hash of at least another portion of the logical address.
15. A method, comprising: generating a first physical address of a first array of volatile memory cells based at least in part on a read command indicating a logical address of the first array of volatile memory cells; reading, based at least in part on the first physical address, a location identifier from a second physical address of a second array of non-volatile memory cells, wherein the second physical address of the second array of non-volatile memory cells is a same as the first physical address of the first array of volatile memory cells; and verifying that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
18. A method, comprising: generating a first physical address of a first array of volatile memory cells based at least in part on decoding a logical address of the first array of volatile memory cells indicated by a write command; reading a location identifier from a second physical address of a second array of non-volatile memory cells based at least in part on generating the first physical address, wherein the second physical address of the second array of non-volatile memory cells is the same as the first physical address of the first array of volatile memory cells; determining, based at least in part on reading the location identifier, whether the location identifier corresponds to the logical address; and verifying that the first physical address was generated without one or more errors based at least in part on determining that the location identifier corresponds to the logical address.
16. The method of claim 15, further comprising: reading a data word from the first physical address of the first array of volatile memory cells based at least in part on generation of the first physical address, wherein reading the location identifier comprises reading a location indicia from the second physical address of the second array of non-volatile memory cells, wherein verifying that the first physical address was generated without one or more errors is based at least in part on reading the data word from the first array of volatile memory cells and determining that the location indicia corresponds to the logical address.
17. The method of claim 16, wherein: the location indicia is read before reading the data word, or the location indicia is read after reading the data word.
18. The method of claim 16, wherein the location indicia is read concurrently with reading the data word.
19. The method of claim 16, wherein determining that the location indicia corresponds to the logical address comprises: determining that the location indicia corresponds to the logical address based at least in part on determining that the location indicia corresponds to the second physical address.
20. The method of claim 18, further comprising: writing data associated with the write command to the first physical address based at least in part on generating the first physical address.
20. The method of claim 16, wherein the location indicia comprises: the first physical address, a column of the first physical address, a row of the first physical address, a hash of the first physical address, or any combination thereof; or the logical address, a column of the logical address, a row of the logical address, a hash of the logical address, or any combination thereof.
17. The apparatus of claim 10, wherein the first location identifier comprises a first hash of at least a portion of the logical address and the second location identifier comprises a second hash of at least another portion of the logical address.
Allowable Subject Matter
Claims 1-20 are allowed over the prior art for the same reasons given in the parent application 18/306,110.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132