Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/9/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 3/27/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 26 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the computer-readable medium is defined in the specification as a signal or carrier wave (par. 0131: “Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave.”). Applicant is advised to amend the claim to exclude such transitory embodiments by adding “non-transitory” to the computer-readable storage medium, which would render the claim statutory.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11, 14-18, and 22-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Long (US 11574381 B2).
Regarding claim 1, Long teaches an apparatus for graphics processing (col. 75, lines 22-23: “In one embodiment, a processing apparatus may be provided.”), comprising:
at least one memory (col. 75, lines 23-28: “The processing apparatus may comprise a first unit to receive a plurality of graphics data comprising a first graphics data, each of the plurality of graphics data mapped to a corresponding buffer in a graphics processing unit (GPU) memory, wherein the first graphics data is mapped to a first buffer in the GPU memory.”); and
at least one processor coupled to the at least one memory (col. 75, lines 23-28, as above) and, based at least in part on information stored in the at least one memory, the at least one processor is configured to:
obtain an indication of a graphics operation, wherein the graphics operation is associated with data in a data block (col. 75, lines 23-28, as above);
determine whether a value for at least some data in the data block is identical to a value for at least some other data in the data block (col. 74, lines 14-17: “At block 3212, the second graphics data may be remapped, by the processing unit, to the first buffer if the content of the first buffer is identical with content of the second buffer.”); and
refrain from executing the at least some data in the data block based on the value for the at least some data in the data block being identical to the value for the at least some other data in the data block (col. 74, lines 17-23: “In this way, buffers mapped by other graphics data may each be compared with an existing buffer mapped by the existing graphics data and the graphics data may be remapped if the result of comparison shows that the buffer is identical to the existing buffer. Since the buffer identical to the existing buffer is removed from the GPU memory, memory space may be saved.”).
Regarding claim 2, Long teaches the apparatus of claim 1, wherein to determine whether the value for the at least some data in the data block is identical to the value for the at least some other data in the data block, the at least one processor is configured to:
determine whether a source operand for the at least some data in the data block is identical to a source operand for the at least some other data in the data block (col. 74, lines 4-7: “At block 3208, a checksum of the first buffer may be compared, by the data removal logic, with a checksum of the second buffer if the data attribute of the first graphics data is identical with the data attribute of the second graphics data.”).
Regarding claim 3, Long teaches the apparatus of claim 2, wherein to determine whether the source operand for the at least some data in the data block is identical to the source operand for the at least some other data in the data block, the at least one processor is configured to:
determine that the source operand for all of the data in the data block is identical (col. 74, lines 4-7, as above).
Regarding claim 4, Long teaches the apparatus of claim 3, wherein to determine that the source operand for all of the data in the data block is identical, the at least one processor is configured to:
determine that the source operand for all of the data in the data block is identical in multiple dimensions (col. 73, lines 64-67: “In one embodiment, the data attribute may comprise one or more of width, height, format, layout, name uniqueness and being read-only.”).
Regarding claim 5, Long teaches the apparatus of claim 1, wherein the at least one processor is further configured to:
generate metadata for the at least some data in the data block based on the value for the at least some data in the data block being identical to the value for the at least some other data in the data block (col. 76, line 59 – col. 77, line 2: “Example 1 includes a method, comprising: receiving a plurality of graphics data comprising a first graphics data, each of the plurality of graphics data mapped to a corresponding buffer in a Graphics Processing Unit (GPU) memory, wherein the first graphics data is mapped to a first buffer in the GPU memory; receiving a second graphics data mapped to a second buffer in the GPU memory; comparing the first buffer mapped by the first graphics data with the second buffer mapped by the second graphics data; and remapping the second graphics data to the first buffer if the first buffer is identical with the second buffer.”).
Regarding claim 6, Long teaches the apparatus of claim 5, wherein to generate the metadata for the at least some data in the data block based on the value for the at least some data being identical to the value for the at least some other data, the at least one processor is configured to:
generate a mask for the at least some data in the data block based on the value for the at least some data being identical to the value for the at least some other data (col. 21, lines 62-66: “In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call with a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save/restore area pointer (CSRP).”).
Regarding claim 9, Long teaches the apparatus of claim 6, wherein to generate the mask for the at least some data in the data block based on the value for the at least some data being identical to the value for the at least some other data, the at least one processor is configured to:
generate the mask for all of the data in the data block based on all of a set of fibers within the data block being identical (col. 50, lines 27-32: “Each execution unit in execution units 1808A-1808N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions.”; col. 39, lines 50-64: “ A data center can utilize a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds can be coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center may, in use, pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and/or artificial intelligence accelerators, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local.”).
Regarding claim 10, Long teaches the apparatus of claim 9, wherein to generate the mask for all of the data in the data block, the at least one processor is configured to:
group all of the data in the data block into a same group based on all of the data in the data block being identical (col. 52, lines 62-66: “In one embodiment, arrays of multiple instances of the graphics execution unit 1808 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping.”).
Regarding claim 11, Long teaches the apparatus of claim 5, wherein to the generate metadata for the at least some data in the data block based on the value for the at least some data being identical to the value for the at least some other data, the at least one processor is configured to:
generate the metadata for all of the data in the data block based on all of the data in the data block being identical (col. 72, lines 25-31: “After comparison among the plurality of buffers 3022-3046 is performed, it may be determined that the buffer 3042 is identical with the buffer 3022, and the buffer 3044 is identical with the buffer 3024. Then, the graphics data 3012 may be remapped to the buffer 3022, and the graphics data 3014 may be remapped to the buffer 3024.”).
Regarding claim 14, Long teaches the apparatus of claim 1, wherein to refrain from executing the at least some data in the data block based on the value for the at least some data in the data block being identical to the value for the at least some other data in the data block, the at least one processor is configured to:
refrain from executing all of the data in the data block based on the value for all of the data in the data block being identical (col. 72, lines 32-38: “In this way, buffers mapped by other graphics data may each be compared with an existing buffer mapped by the existing graphics data and the graphics data may be remapped if the result of comparison shows that the buffer is identical to the existing buffer. Since the buffer identical to the existing buffer is removed from the GPU memory, memory space may be saved.”).
Regarding claim 15, Long teaches the apparatus of claim 14, wherein to refrain from executing all of the data in the data block, the at least one processor is configured to:
refrain from temporally executing all of the data in the data block (col. 68, lines 41-47: “If the data removal logic 2930 determines that the buffer 2916 is identical with the buffer 2926, the data removal logic 2930 may notify the runtime logic 2924 that the buffer 2926 is a duplicate of the buffer 2916, e.g., by sending a message. Then the runtime logic 2924 may remap the graphics data 2922 to the buffer 2916, and the buffer 2926 may be removed from the GPU memory 2905.”); or
refrain from spatially executing all of the data in the data block (col. 67, lines 16-24: “ In a cloud gaming scenario, the graphics materials corresponding to the graphics data 2712 and 2722 such as texture may be very large and the content thereof may be duplicated. Therefore, the GPU memory 2705 is wasted since the graphics data 2712 and 2722 consume memory space of the GPU memory 2705 for the duplicated data. More game instances can be supported if the duplicated data can be removed from the GPU memory 2705, which improves the utilization of the GPU memory 2705.”).
Regarding claim 16, Long teaches the apparatus of claim 14, wherein to refrain from executing all of the data in the data block, the at least one processor is configured to:
refrain from executing all of the data in the data block in multiple dimensions (col. 67, lines 16-24, as above in claim 15 rejection).
Regarding claim 17, Long teaches the apparatus of claim 1, wherein to refrain from executing the at least some data in the data block, the at least one processor is configured to at least one of:
skip executing the at least some data in the data block (col. 74, lines 17-23, as above in claim 1 rejection);
skip executing all of the data in the data block (col. 59, lines 7-11: “Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command 2212 can be used for pipeline synchronization or before placing the graphics processor into a low power state.”); or
execute less than all of the data in the data block (col. 74, lines 17-23, as above in claim 1 rejection).
Regarding claim 18, Long teaches the apparatus of claim 1, wherein to refrain from executing the at least some data in the data block, the at least one processor is configured to:
dispatch data for the at least some other data in the data block (col. 51, lines 31-39: “To execute the shader program, the shader processor 1802 dispatches threads to an execution unit (e.g., 1808A) via thread dispatcher 1804. In some embodiments, shader processor 1802 uses texture sampling logic in the sampler 1810 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.”); and
skip executing the at least some data in the data block (col. 74, lines 17-23, as above in claim 1 rejection).
Regarding claim 22, Long teaches the apparatus of claim 1, wherein to determine whether the value for the at least some data in the data block is identical to the value for the at least some other data in the data block, the at least one processor is configured to:
determine that the value for all of the data in the data block is identical (col. 74, lines 14-17, as above in claim 1 rejection).
Regarding claim 23, Long teaches the apparatus of claim 1, wherein the at least one processor is further configured to:
output an indication of the refrainment from executing the at least some data in the data block (col. 59, lines 35-37: “In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication.”).
Regarding claim 24, Long teaches the apparatus of claim 23, wherein to output the indication of the refrainment from executing the at least some data in the data block, the at least one processor is configured to:
transmit the indication of the refrainment from executing the at least some data in the data block (col. 62, lines 27-29: “Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 2450 or wireless connection 2460.”); or
store the indication of the refrainment from executing the at least some data in the data block (col. 62, lines 24-27: “The IP core design can be stored for delivery to a 3.sup.rd party fabrication facility 2465 using non-volatile memory 2440 (e.g., hard disk, flash memory, or any non-volatile storage medium).”).
Claim 25 is substantially similar to claim 1, and differs primarily in that it teaches a method rather than an apparatus. As such, it is rejected on similar grounds to claim 1.
Claim 26 is substantially similar to claim 1, and differs primarily in that it teaches a computer-readable medium rather than an apparatus. As such, it is rejected on similar grounds to claim 1.
Allowable Subject Matter
Claims 7-8, 12-13, and 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A BARHAM whose telephone number is (571)272-4338. The examiner can normally be reached Mon-Fri, 8:30am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu, can be reached at (571) 272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN ALLEN BARHAM/Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613
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