Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-7-9 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaharabany et al., US 2015/0301763 [hereinafter, Shaharabany] in view of Natarajan (US 2020/0167089).
As for claims 1, 6, 9, 14 and 16:
Shaharabany discloses a storage system [see figure 1] and a method of adjusting an amount of differing solid state memory types thereof. The storage system comprising: NVRAM (nonvolatile random-access memory) comprising differing solid state memory types [e.g., nonvolatile memory 120 having SLC and MLC portions; see also para. 0022]; and a processor [e.g., processor 113], to perform a method, comprising: monitoring an incoming workload for a storage system [e.g., burst modes associated with workloads; see figure 4, step 430; para. 0028]; and adjusting an amount of differing solid state memory types within a buffer of the storage system based on the monitoring [see again para. 0022, the SLC and MLC are dynamically allocated depending on which burst mode is selected; see also para. 0025].
Shaharabany, however, does not disclose that the NVM 120 is being used as a buffer.
Still, it is no more than a matter of “field of use”. For example, the storage system can be used in a cloud-based storage system for buffering data from the cloud. Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date to utilize the Shaharabany NMV memory 120 for buffering data from a cloud-based storage system.
Shaharabany does not explicitly teach, but Natarajan teaches wherein adjusting the amount of differing solid state memory types comprises dynamically moving a boundary between the differing solid state memory types within the buffer in response to the monitoring. [[0030] The SLC region 41 may include a static SLC (SSLC) portion and a dynamic SLC (DSLC) portion. FIG. 4A shows a nominal baseline configuration, while FIG. 4B shows an increased size of the DSLC portion relative to the baseline and FIG. 4C shows a decreased size of the DSLC portion relative to the baseline.]
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention to combine the adaptive storage system/method of Shaharabany with the dynamic single-cell, multi-cell memory system of Natarajan. The rationale for doing so would have been that adjusting the boundary between SLCs and MLCs would provide a reliable, well-known means to control and manage the ratio between SLC and MLC to efficiently handle memory access commands in data storage/retrieval system with a reasonable expectation of success.
As for claims 7 and 17:
The further claimed limitation of “wherein the differing solid state memory types comprise a more durable solid state memory and a less durable solid state memory” is also taught by Shaharabany through the SLC portion and the MLC portion of the NVM 120 since the SLC is more durable comparing to the MLC [Official Notice is hereby taken].
As for claim 18:
The further claimed limitation of “wherein the differing solid state memory types comprise Quad level cell (QLC) memory and single level cell (SLC) memory” is also suggested by Shaharabany. This is because QLC is one of the MLC, as commonly known in the art.
As for claims 8, 15 and 19:
The further claimed limitation of “wherein the method further comprises: reversing the adjusting the amount of differing solid state memory types within the buffer once data associated with the incoming workload is flushed to flash memory of the storage system” is also suggested by Shaharabany. This is because the SLC and the MLC portions are dynamically allocated based on the workload (i.e., burst modes). Clearly, when the command buffer is empty, the SLC and the MLC portions will be reversed back to it default setting.
As for claim 20:
The further claimed limitation of “wherein the NVRAM is contained within a storage device and wherein the storage system comprises multiple storage devices on a blade having the processor” would follow necessarily when the Shaharabany storage system is being used in a cloud-based storage system, as mentioned above.
Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaharabany and Natarajan (US 2020/0167089), further in view of Foster, II et al., US 2022/0050728 [hereinafter, Foster]
Shaharabany disclose a method as mentioned above.
Shaharabany, however, does not disclose that the monitoring comprises detecting a change associated with types of data associated with the workload.
Foster teaches that one of the dimensions associated with the workload is data type [see para. 0013].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Shaharabany and Natarajan’s storage controller to detecting change associated with types of data associate with the workload simply because different data types require different workloads, as taught by Foster.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaharabany, Natarajan (US 2020/0167089) and Foster and further in view of Mahesh, US 2021/0117117 [herein after, Mahesh].
Shaharabany- foster combination discloses a method as mentioned above.
The combination, however, does not disclose that wherein the change comprises an increase in latency sensitive writes and wherein the method comprises converting a portion of solid state memory in the buffer from Quad level cell (QLC) memory to single level cell (SLC) memory.
Mahesh teaches that SLC is used for serving high performance/low latency storage need while using MLC for high capacity storage needs [see para. 0081].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Shaharabany-Natarajan-Foster storage controller to convert a portion of solid state memory in the buffer from Quad level cell (QLC) memory to single level cell (SLC) memory when there is an increase in latency sensitive writes. This is because using SLC portion to serve the latency sensitive write would relatively reduce the latency, as taught by Mahesh.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaharabany and Natarajan (US 2020/0167089) and Foster and further in view of Natarajan et al., US 2024/0394193 [hereinafter, Natarajan].
Shaharabany-Foster combination discloses a method as mentioned above in the rejection of claim 2.
The combination, however, does not disclose that the change comprises an increase in large size writes and wherein the method comprises converting a portion of solid state memory in the buffer from SLC memory to QLC memory.
Natarajan teaches that when data stream is large in size the data is written into MLC portion and when the data is a small volume the data is written into SLC portion [see para. 0041].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Shaharabany-Natarajan-Foster storage controller to convert a portion of solid state memory in the buffer from SLC memory to QLC memory when there in an increase in large size writes. This is because for large write size, the data is written directly to the MLC portion, as taught by Natarajan.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaharabany and Natarajan (US 2020/0167089), further in view of Araki et al., US 2010/0115183 [hereinafter, Araki].
Sharabany discloses a methos as mentioned above.
Shaharabany, however, does not disclose the operation of monitoring wear levels of the differing solid state memory types; and converting to a more durable solid state memory type as a wear level of one of the differing solid state memory types reaches a threshold value for a less durable solid sates memory type.
Araki teaches that memory blocks with high rewrite frequency is allocated to SLC section and that blocks with low rewrite frequency are allocated to MLC section [see para. 0072].
It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the claimed invention to configure the Shaharabany and Natarajan’s storage controller to convert MLC block to SLC block when the rewrite frequency is equal or larger than a threshold, as taught by Araki.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
You (US 2022/0083258): discloses storage system with dynamic adjustment capabilities between SLC and TLC regions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133
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