DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter because
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
With respect to claim 9, the claim recites “A computer readable storage medium to allow a computer to execute …" The applicant’s specification does not limit the phrase "computer readable storage medium” to include only non-statutory matter. Further, the Examiner further notes that the words "storage", “tangible” and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter. The dependent claims inherit the deficiencies of their respective independent claim.
The Examiner suggests amending the claim(s) to include a “non-transitory computer readable storage medium” to overcome the rejection above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 9, 10, and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Puthoor et al. 20230195645 herein Puthoor.
Per claim 1, Puthoor discloses: determining a data operand for processing-in-memory to be shared with a processor-in-memory, by a CPU; (fig. 1 & 4, ¶0057; receiving 412 a PIM command that includes a virtual address indexing an entry in the virtual instruction store. A translation mechanism determines whether a valid mapping of the virtual address to a physical address exists. If such a valid mapping does not exist, the translation fails and the process from which the PIM instruction was received is effectively prohibited from accessing PIM resources. If there is a valid virtual-to-physical mapping, the translation mechanism translates 414 the virtual address to a physical address.) searching a page table corresponding to the data operand from a memory, by the CPU; (fig. 1 & 4, ¶0057; A translation mechanism determines whether a valid mapping of the virtual address to a physical address exists. If such a valid mapping does not exist, the translation fails and the process from which the PIM instruction was received is effectively prohibited from accessing PIM resources. If there is a valid virtual-to-physical mapping, the translation mechanism translates 414 the virtual address to a physical address.) defining an address space of the determined data operand in an operand address space which is divided into a plurality of sub spaces and generating an operand page table according to the defined address space, by the CPU; (fig. 4 comp 404, ¶0053-0054; the configuration context includes a virtual instruction store with a number of entries. Each of the entries includes a PIM instruction opcode. A ‘virtual instruction store’ is a virtualization of a local instruction store of a PIM device. That is, the virtual instruction store is a data structure in virtual memory that can be mapped to a physical, local instruction store (LIS) utilized by the PIM device. Each entry of a virtual instruction store include a PIM instruction opcode to be used in executing PIM instructions offloaded to the PIM device …..allocating 404 the virtual address space to the process. Allocating 404 the virtual address includes mapping 406 a physical address space of configuration registers of the PIM device to the virtual address space only if the physical address space is not mapped to another process's virtual address space.) generating memory internal address translating information for the determined data operand and transmitting the memory internal address translating information to the processor- in-memory, by the CPU, wherein the memory internal address translating information includes a start virtual address, an end virtual address, a start operand address, an operand page table basic address, and operand page table type information (fig. 4 comp 412-420, ¶0033-34, ¶0057-59; The PIM device then utilizes the translated address (the physical address) to retrieve 416, from the entry of the local instruction store, a PIM instruction opcode. The opcode specifies an operation to be performed by the PIM device… a PIM command targeting a virtual memory address of a memory buffer of the PIM device and translating 420 the virtual memory address to a physical address of one of the memory buffers only if the physical address is included in one of the memory pages assigned to the process. The memory buffer stores the operand of the instruction. A translation mechanism translates 420 the virtual memory address to a physical address only if the requesting process has valid mappings) and determining a physical address for the determined data operand, using the operand page table and the memory internal address translating information, by the processor-in-memory (fig. 4 comp 420. ¶0059; receiving 418, from the process, a PIM command targeting a virtual memory address of a memory buffer of the PIM device and translating 420 the virtual memory address to a physical address of one of the memory buffers only if the physical address is included in one of the memory pages assigned to the process. The memory buffer stores the operand of the instruction. A translation mechanism translates 420 the virtual memory address to a physical address only if the requesting process has valid mappings. The translation mechanism inspects memory page attributes to determine whether the memory page holding the virtual memory address is assigned to the process ID of the requesting process. If it is, the translation can proceed.).
Per claim 4, Purhoor discloses: wherein the operand address space which is divided into the plurality of sub spaces has a distribution which is spaced apart from each other in a virtual address space and an operand page table structure is different according to the sub space (¶0035; Each PIM command carries a target address that is used to direct it to the appropriate PIM unit(s) as well as the PIM instruction to be performed. An execution unit 150 can operate on a distinct subset of the physical address space. When a PIM command reaches the execution unit 150, it is serialized with other PIM commands and memory accesses to DRAM targeting the same subset of the physical address space).
Per claim 5, Purhoor discloses: wherein the processor-in-memory further includes an address translator and the address translator of the processor-in-memory determines a physical address for the determined data operand regardless of a structure of the CPU (fig. 4 comp 412-420, ¶0057-59; The PIM device then utilizes the translated address (the physical address) to retrieve 416, from the entry of the local instruction store, a PIM instruction opcode. The opcode specifies an operation to be performed by the PIM device… a PIM command targeting a virtual memory address of a memory buffer of the PIM device and translating 420 the virtual memory address to a physical address of one of the memory buffers only if the physical address is included in one of the memory pages assigned to the process. The memory buffer stores the operand of the instruction. A translation mechanism translates 420 the virtual memory address to a physical address only if the requesting process has valid mappings).
Claim 9 is the CRM claim corresponding to the method claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Per claim 10, Puthoor discloses: a CPU and a memory which stores execution instructions for translating a virtual address and includes a processor-in-memory, wherein steps performed by the CPU by executing the execution instructions include:(fig. 1, ¶0031; In the implementation in which the processor cores operate according to an extended ISA that explicitly supports PIM instructions, a PIM instruction is completed by the processor cores 102, 104, 106, 108 when virtual and physical memory addresses associated with the PIM instruction are generated, operand values in processor registers become available, and memory consistency checks have completed.) determining a data operand for processing-in-memory to be shared with a processor-in-memory, by the CPU; (fig. 1 & 4, ¶0057; receiving 412 a PIM command that includes a virtual address indexing an entry in the virtual instruction store. A translation mechanism determines whether a valid mapping of the virtual address to a physical address exists. If such a valid mapping does not exist, the translation fails and the process from which the PIM instruction was received is effectively prohibited from accessing PIM resources. If there is a valid virtual-to-physical mapping, the translation mechanism translates 414 the virtual address to a physical address.) searching a page table corresponding to the data operand from a memory, (fig. 1 & 4, ¶0057; A translation mechanism determines whether a valid mapping of the virtual address to a physical address exists. If such a valid mapping does not exist, the translation fails and the process from which the PIM instruction was received is effectively prohibited from accessing PIM resources. If there is a valid virtual-to-physical mapping, the translation mechanism translates 414 the virtual address to a physical address.) defining an address space of the determined data operand in an operand address space which is divided into a plurality of sub spaces according to a number or a size of operand page tables, and generating an operand page table according to the defined address space, (fig. 4 comp 404, ¶0053-0054; the configuration context includes a virtual instruction store with a number of entries. Each of the entries includes a PIM instruction opcode. A ‘virtual instruction store’ is a virtualization of a local instruction store of a PIM device. That is, the virtual instruction store is a data structure in virtual memory that can be mapped to a physical, local instruction store (LIS) utilized by the PIM device. Each entry of a virtual instruction store include a PIM instruction opcode to be used in executing PIM instructions offloaded to the PIM device …..allocating 404 the virtual address space to the process. Allocating 404 the virtual address includes mapping 406 a physical address space of configuration registers of the PIM device to the virtual address space only if the physical address space is not mapped to another process's virtual address space.) the processor-in-memory determines a physical address for the determined data operand, using the operand page table (fig. 4 comp 420. ¶0059; receiving 418, from the process, a PIM command targeting a virtual memory address of a memory buffer of the PIM device and translating 420 the virtual memory address to a physical address of one of the memory buffers only if the physical address is included in one of the memory pages assigned to the process. The memory buffer stores the operand of the instruction. A translation mechanism translates 420 the virtual memory address to a physical address only if the requesting process has valid mappings. The translation mechanism inspects memory page attributes to determine whether the memory page holding the virtual memory address is assigned to the process ID of the requesting process. If it is, the translation can proceed.).
Claim 13 is the apparatus claim corresponding to the method claim 5 and are rejected under the same reasons set forth in connection with the rejection of claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-8 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Puthoor in view of Ramakrishnan 20140006684 herein Ramakrishanan.
Per claim 6, Puthoor discloses address translation means to access a page table table or TLB but does not specifically disclose: wherein the address translator includes a translation lookaside buffer (TLB) which caches page table information and a page table walker (PTW) which accesses a page table stored in the memory to fetch mapping information.
However, Ramakrishnan discloses: wherein the address translator includes a translation lookaside buffer (TLB) which caches page table information and a page table walker (PTW) which accesses a page table stored in the memory to fetch mapping information (fig. 6, ¶0072; hen a physical address translation is not found in the TLB, a page walk may be performed by the ucode to obtain the linear-to-physical translation from the page table. The usual page table contains a direct translation from linear address to page physical address of the OS-visible memory. However, in the case of two- or three-level memory subsystems, the near memory levels may not be OS-visible and hence may require an additional level of translation from the OS-visible page physical addresses to near memory addresses).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Puthoor and Ramakrishnan’s near memory cache access because of its proximity to the processor. Ramakrishnan improves the latency of data accesses (¶0016).
Per claim 7, Ramakrishnan discloses: wherein prior to searching whether the page table corresponding to the data operand is in the memory, the CPU searches whether the page table is stored in the translation lookaside buffer first (fig. 6, ¶0072; When a physical address translation is not found in the TLB, a page walk may be performed by the ucode to obtain the linear-to-physical translation from the page table. The usual page table contains a direct translation from linear address to page physical address of the OS-visible memory. However, in the case of two- or three-level memory subsystems, the near memory levels may not be OS-visible and hence may require an additional level of translation from the OS-visible page physical addresses to near memory addresses).
Per claim 8, Ramakrishnan discloses: wherein the page table operator searches the page table stored in the memory with reference to an address of a page table stored in a register of the CPU (fig. 6, ¶0072; When a physical address translation is not found in the TLB, a page walk may be performed by the ucode to obtain the linear-to-physical translation from the page table. The usual page table contains a direct translation from linear address to page physical address of the OS-visible memory. However, in the case of two- or three-level memory subsystems, the near memory levels may not be OS-visible and hence may require an additional level of translation from the OS-visible page physical addresses to near memory addresses).
Claim 14-15 is the apparatus claims corresponding to the method claims 6-8 and are rejected under the same reasons set forth in connection with the rejection of claims 6-8.
Per claim 16, the Puthoor discloses: wherein the address translator further includes a virtual address-operand address translator (VOC) (fig. 4 comp 404, ¶0053-0054; the configuration context includes a virtual instruction store with a number of entries. Each of the entries includes a PIM instruction opcode. A ‘virtual instruction store’ is a virtualization of a local instruction store of a PIM device. That is, the virtual instruction store is a data structure in virtual memory that can be mapped to a physical, local instruction store (LIS) utilized by the PIM device. Each entry of a virtual instruction store include a PIM instruction opcode to be used in executing PIM instructions offloaded to the PIM device).
Puthoor does not specifically disclose: and a walker cache and the page table walker obtains information for translating an operand address into a physical address using information stored in the walker cache based on the operand address information received from the VOC.
Ramakrishnan discloses: and a walker cache and the page table walker obtains information for translating an operand address into a physical address using information stored in the walker cache based on the operand address information received from the VOC (fig. 4 & 6, ¶0072; When a physical address translation is not found in the TLB, a page walk may be performed by the ucode to obtain the linear-to-physical translation from the page table. The usual page table contains a direct translation from linear address to page physical address of the OS-visible memory. However, in the case of two- or three-level memory subsystems, the near memory levels may not be OS-visible and hence may require an additional level of translation from the OS-visible page physical addresses to near memory addresses).
Response to Arguments
Applicant's arguments filed 7/22/26 have been fully considered but they are not persuasive.
The applicant argues: Puthoor is completely silent on generating a specialized set of memory internal address translating information comprising the five distinct parameters now expressly recited by claims 1 and 10, as amended: (1) a start virtual address, (2) an end virtual address, (3) a start operand address, (4) an operand page table basic address, and (5) operand page table type information. At most, Puthoor describes a translation mechanism that determines whether a valid virtual-to-physical mapping exists and, if so, translates a virtual address to a physical address that indexes an entry of a local instruction store. See Puthoor, paragraphs [0057]-[0059].
The examiner respectfully disagrees and asserts that the claim limitation merely requires parameters derived from virtual addresses, physical addresses, operands, operand page tables and addresses. The claims do not set forth any specificity of the start and end address or the page table type other than it is information used to translate a virtual address into a physical address. Per the applicant’s specification, the start and end addresses are merely a derivative of the virtual address range. It serves as an index or start position in the address space and translation tables. Further, the operand type is merely a means to identify the operand type such as a register/local store. While the cited portions don’t explicitly use the same terms as the claim, the functionality of the claim is taught by Puthoor. If it is the applicant’s intent to claim a specific derivative of the virtual address or a specific process using the virtual address to translate a virtual-physical mapping the applicant is encouraged to do so without introducing new matter. The examiner asserts that the translation process of Puthoor describes a translation process wherein the virtual address is translated into the virtual instruction store (¶0033-34). Further, using the virtual address and index into the opcodes and operant of the PIM instruction is taught (¶0015).
The applicant argues: "generating memory internal address translating information for the determined data operand and transmitting the memory internal address translating information to the processor-in-memory, by the CPU, wherein the memory internal address translating information includes a start virtual address, an end virtual address, a start operand address, an operand page table basic address, and operand page table type information" and "the processor-in-memory determines a physical address for the determined data operand, using the operand page table and the memory internal address translating information".
The examiner respectfully disagrees and asserts that the claim limitation merely requires parameters derived from virtual addresses, physical addresses, operands, operand page tables and addresses. The claims do not set forth any specificity of the start and end address or the page table type other than it is information used to translate a virtual address into a physical address. Per the applicant’s specification, the start and end addresses are merely a derivative of the virtual address range. It serves as an index or start position in the address space and translation tables. Further, the operand type is merely a means to identify the operand type such as a register/local store. While the cited portions don’t explicitly use the same terms as the claim, the functionality of the claim is taught by Puthoor. If it is the applicant’s intent to claim a specific derivative of the virtual address or a specific process using the virtual address to translate a virtual-physical mapping the applicant is encouraged to do so without introducing new matter. The examiner asserts that the translation process of Puthoor describes a translation process wherein the virtual address is translated into the virtual instruction store (¶0033-34). Further, using the virtual address and index into the opcodes and operant of the PIM instruction is taught (¶0015). Ramakrishnan is relied upon to teach the specific TLB and the page table walker to fetch information. The combine teachings of Puthoor and Ramakrishnan disclose generating memory internal address translating information for the determined data operand and transmitting the memory internal address translating information to the processor-in-memory, by the CPU, wherein the memory internal address translating information includes a start virtual address, an end virtual address, a start operand address, an operand page table basic address, and operand page table type information.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
