DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 11/27/2024 are acceptable for examination purposes.
Information Disclosure Statement
6. The references listed in the information disclosure statement (IDS) submitted on 11/27/2024 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 4, 9-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. In regards to claim 4, the claim recites “generate a fourth byte comprising a second portion of the first byte and a second portion of the second byte; and transmit, using a second one lane of the two or more lanes of the die-to-die system, the fourth byte.” There is insufficient antecedent basis in the claim by using the phrase “a fourth byte” because the claims 1 and 4 recite first byte, second byte, and fourth byte, but are silent regarding to third byte. Please clarify. In regards to claim 9, the claim recites " receive data to transmit using a die-to-die system." This feature is ambiguous because it’s unclear in the claim what the kind of the information that need to be transmitted. “Emphasis added.” Other independent claim 12 recites similar limitations of claim 1. Therefore, is rejected for the same reason of claim 1. Dependent claims 5-6, 9-11 and 13-20 depend from the base claims 4, 9 and 12 respectively and inherently include limitations therein and therefore are rejected under 35 USC 112, 2nd paragraph as well.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 9-11 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Iyer et al. (US 20180196710 A1) "herein after as Iyer."
As per claim 9:
Iyer teaches or discloses an apparatus comprising: a die (see Figs. 5 and 12) comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520; and Fig. 12 transmitting device 105 & receive device 1210): receive data to transmit using a die-to-die system (see paragraph [0093], the first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215 ----The second device 1210 can include logic to receive the flit and decode, or otherwise identify, the flit, including header values, slot values, and the CRC value (e.g., using CRC checking logic 1230)); generate error correction information for the data (see paragraph [0094], herein a receiving device can utilize a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device can regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value with the received CRC value (e.g., using CRC checking logic 1230) to determine bit errors; and [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes); encode the data and the error correction information to generate encoded information (see paragraph [0069], herein the stream signal can be an encoded signal (e.g., 1 byte of data for a byte time period window; and paragraph [0093], herein Each flit can include a CRC value calculated and encoded using a CRC generator 1225); and transmit, using the die-to-die system, at least a portion of the encoded information (see paragraph [0069], herein that is encoded to identify the protocol that applies to data being sent during the same time period window); and paragraph [0093], herein the flits can be sent over the link 1215 to the second receiving device 1210).
As per claim 11:
Iyer teaches that wherein the at least one circuit is configured to configured to generate the error correction information using an error correction code (see paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes, determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lane).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 1-7 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer et al. (US 2018/0196710 A1) "herein after as Iyer" in view of Lanka et al. (2021/0004347 A1) "herein after as Lanka."
As per claim 1:
Iyer substantially teaches or discloses an apparatus comprising (see Fig. 5): a die comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520): receive a first byte mapped to a first lane of two or more lanes of a die-to-die system (see paragraph [0092], herein the CRC polynomial can be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link, and paragraph [0132], herein receive first data on a plurality of data lanes of a physical link, receive a stream signal corresponding to the first data on a stream lane identifying a type of the first data); receive a second byte mapped to a second lane of the two or more lanes of the die-to-die system (see paragraph [0132], herein receive second data on at least a portion of the plurality of data lanes, receive a stream signal corresponding to the second data on the stream lane identifying a type of the second data); transmit, using one lane of the two or more lanes of the die-to-die system, a portion of the first byte (see paragraph [0051], herein an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received).
Iyer does not explicitly teach transmit, using the one lane of the two or more lanes of the die-to-die system, a portion of the second byte.
However, Lanka in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0115], herein which illustrates one or more operations for determining whether a second criterion is met in the other embodiment of an approximate majority vote based DBI technique. At 1322, majority vote logic is applied to a second set of bits (second bits) of a plurality of bits of original data to be transmitted in a new clock cycle; and paragraph [0188], herein the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer with the teachings of Lanka by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
As per claim 2:
Iyer teaches that wherein the one lane of the two or more lanes of the die-to-die system is the first lane of the two or more lanes of the die-to-die system (see paragraph [0069], herein data sent on each of the lanes of the MCPL can be strictly aligned to the strobe signal, and paragraph [0096], herein the bit-to-lane mapping module 1260 can determine the lanes used in the sending of a particular flit and thereby determine the bit ordering used during the transmission to determine the specific lane on which each flit bit was sent).
As per claim 3:
Iyer teaches that wherein the one lane of the two or more lanes of the die-to-die system is a third lane of the two or more lanes of the die-to-die system (see paragraph [0069], herein data sent on each of the lanes of the MCPL can be strictly aligned to the strobe signal, and paragraph [0096], herein the bit-to-lane mapping module 1260 can determine the lanes used in the sending of a particular flit and thereby determine the bit ordering used during the transmission to determine the specific lane on which each flit bit was sent).
As per claim 4:
Iyer teaches that wherein the portion of the first byte is a first portion of the first byte, the portion of the second byte is a first portion of the second byte, the one lane of the two or more lanes of the die-to-die system is a first one lane of the two or more lanes of the die-to-die system (see paragraph [0101], herein illustrated in FIG. 13C, an example bit mapping of link-to-link packets (e.g., LLP packets) sent over an example MCPL is shown. LLPs can be 4 bytes each and each LLP (e.g., LLP0, LLP1, LLP2, etc.) can be sent four consecutive times), and the at least one circuit is configured to: generate a fourth byte comprising a second portion of the first byte and a second portion of the second byte; and transmit, using a second one lane of the two or more lanes of the die-to-die system, the fourth byte (see paragraph [0093], herein The first device 1205 can include logic 1220 to generate one or more flits for transmission across the MCPL 1215. A packet, message, or other formulation of data to be sent over the MCPL can comprise one or more flits, and Fig. 12).
As per claim 5:
Iyer teaches that wherein the second one lane of the two or more lanes of the die-to-die system is the second lane of the two or more lanes of the die-to-die system (see paragraph [0056], herein FIG. 5 is a simplified block diagram 500 illustrating an example multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520, and Fig. 5).
As per claim 6:
Iyer teaches that wherein the second one lane of the two or more lanes of the die-to-die system is a third lane of the two or more lanes of the die-to-die system (see paragraph [0056], herein FIG. 5 is a simplified block diagram 500 illustrating an example multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520, and Fig. 5).
As per claim 7:
Iyer teaches that wherein the at least one circuit is configured to: generate error correction information for the portion of the first byte and the portion of the second byte; and transmit, using a lane of the die-to-die system, at least a portion of the error correction information (see paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes, determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lane).
10. Claims 12-14 and 20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer in view in further view of Chen et al. (US 2017/0373714 A1) "herein after as Chen."
As per claim 12:
Iyer substantially teaches or discloses an apparatus comprising (see Fig. 5): a die comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520): receive data to transmit using a die-to-die system (see paragraph [0092], herein the CRC polynomial can be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link, and paragraph [0132], herein receive first data on a plurality of data lanes of a physical link, receive a stream signal corresponding to the first data on a stream lane identifying a type of the first data); generate error correction information for the data (see paragraph [0094], herein a receiving device can utilize a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device can regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value with the received CRC value (e.g., using CRC checking logic 1230) to determine bit errors; paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes); perform a first send operation comprising sending the data using the die-to-die system (see paragraph [0093], herein the first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215. (It should be appreciated that in other instances, device 1210 can send data as the transmitting device over a MCPL to device 1205); receive, based on the first send operation, a request (see paragraph [0098], herein Upon determining that one or more lanes of a link are experiencing problems, based on statistically significant numbers of bit errors determined for the lane from syndrome values 1240 and/or checksum comparison values 1280, a lane manager 1270 can be invoked to perform actions on the lane(s) or instruct one or both of the devices 1205, 1210 to enter a reconfiguration state to correct the issue). Iyer does not explicitly teach perform, based on the request, a second send operation comprising sending a portion of the error correction information
However, Chen in the same the field of endeavor teaches perform, based on the request, a second send operation comprising sending a portion of the error correction information (see paragraph [0027], herein Upon receipt of the error detection code and/or error correction code of the data 402, the second transceiver is configured to perform a check to determine if there is an error in the received data 402. If such an error is detected, the second transceiver is configured to transmit a response 404 to the first transceiver). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer with the teachings of Chen by performing a second send operation comprising sending a portion of the error correction information. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the performing a second send operation comprising sending a portion of the error correction information would have improved error detection and/or correction (see paragraph [0026] of Chen).
As per claim 13:
Iyer teaches that wherein the portion of the error correction information is a first portion of the error correction information, the request is a first request, and the at least one circuit is further configured to: receive, based on the second send operation, a second request; and perform, based on the second request, a third send operation comprising sending a second portion of the error correction information (see paragraph [0146], herein determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lanes. The first and second data can be data of different types or protocols. The first error correction code and the second error correction code can each be instances of a same error correction code type).
As per claim 14:
Iyer teaches that wherein the portion of the error correction information is a first portion of the error correction information, and wherein: the first send operation comprises sending a second portion of the error correction information (paragraph [0132], herein identify a first instance of an error detection code of a particular type in the first data, receive second data on at least a portion of the plurality of data lanes, receive a stream signal corresponding to the second data on the stream lane identifying a type of the second data, and identify a second instance of the error detection code of the particular type in the second data).
As per claim 20:
Iyer teaches that wherein the at least one circuit comprises a buffer configured to store at least a portion of the error correction information (see Fig. 12, CRC generator 1225).
11. Claim 8 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer in view of lanka and in further view of Pan et al. (US 2019/0190655 A1) "herein after as Pan."
As per claim 8:
Iyer-Lanka as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using variable rate coding.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Lanka as combined with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
12. Claim 10 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer in view of Pan et al. (US 2019/0190655 A1)"herein after as Pan."
As per claim 10:
Iyer does not explicitly teach wherein the at least one circuit is configured to configured to generate the error correction information using variable rate coding.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
13. Claims 15-19 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer in view of Chen and in further view of Pan et al. (US 2019/0190655 A1) "herein after as Pan."
As per claim 15:
Iyer-Chen as combined does not explicitly teach determine the first portion of the error correction information based on a coding rate.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to determine the first portion of the error correction information based on a coding rate (see paragraph [0007], herein the WTRU may determine the performance and/or latency requirements based on a capability of a decoder, an information block size, and/or a coding rate and paragraph [0095]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Chen as combined with the teachings of Pan by determining the first portion of the error correction information based on a coding rate. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the determining the first portion of the error correction information based on a coding rate would have improved error correction capability.
As per claim 16:
Iyer-Chen as combined does not explicitly wherein the at least one circuit is configured to generate the error correction information using variable rate coding. However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Chen as combined with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
As per claim 17:
Iyer-Lanka as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using a convolutional code.
However, Pan in the same the field of endeavor teaches to generate the error correction information using a convolutional code (see paragraph [0110], herein Polar coding may outperform other coding schemes such as convolutional codes (e.g., Tail-Biting CC (TBCC) and/or Trellis-Termination CC (TTCC)), LDPC, and/or Turbo codes at small payload sizes (e.g., 20 bits or 40 bits). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Chen as combined with the teachings of Pan by to generating the error correction information using a convolutional code. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using a convolutional code would have improved error correction capability.
As per claim 18:
Iyer-Lanka as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using a turbo code.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using a turbo code (see paragraph (see paragraph [0110], herein Polar coding may outperform other coding schemes such as convolutional codes (e.g., Tail-Biting CC (TBCC) and/or Trellis-Termination CC (TTCC)), LDPC, and/or Turbo codes at small payload sizes (e.g., 20 bits or 40 bits). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Chen as combined with the teachings of Pan by generating the error correction information using a turbo code. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using a turbo code would have improved error correction capability.
As per claim 19:
Iyer-Chen as combined does not explicitly teach wherein the at least one circuit is configured to determine the portion of the error correction information based on a coding rate. However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to determine the first portion of the error correction information based on a coding rate (see paragraph [0007], herein the WTRU may determine the performance and/or latency requirements based on a capability of a decoder, an information block size, and/or a coding rate and paragraph [0095]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer-Chen as combined with the teachings of Pan by determining the first portion of the error correction information based on a coding rate. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the determining the first portion of the error correction information based on a coding rate would have improved error correction capability.
Examiner Notes
14. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
15. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112