DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-13 and 15-20 are presented for examination. Claim 14 is canceled.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Claim Rejections - 35 USC § 112
4. The rejection of claims 4, 9-20 under 35 U.S.C. § 112, second paragraph, is withdrawn in view of applicant's amendments/remarks.
Response to Arguments
5. Applicant’s argument filed on 06/23/2025 with respect to claims 1, 9, and 12 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of “redirect a portion of the second byte to the one lane of the two or more lanes of the die-to-die system.” As recited in claim 1.
The Examiner directs the applicant’s attention that during examination, a claim must be given its broadest reasonable interpretation (BRI) consistent with the specification as it would be interpreted by one of ordinary skill in the art (MPEP 2111). Paragraph [0005] of the applicant’s specification states that “an apparatus may include a die including at least one circuit configured to receive a first byte mapped to a first lane of two or more lanes of a die-to-die system, receive a second byte mapped to a second lane of the two or more lanes of the die-to-die system, transmit,” and in paragraph [0091] describes that “In the interleaving scheme illustrated in FIG. 6, however, bytes from the byte mappers 611 may be input to an interleaving function 613 that may generate remapped bytes 614-0, 614-1, 614-2, and/or 614-3 having revised bitmaps as illustrated in FIG. 6. For example, bits 0 and 4 from byte mappers 611-0, 611-1, 611-2, and/or 611-3 may be combined in remapped byte 614-0. Similarly, bits 1 and 5 may be combined in remapped byte 614-1.” So, the Examiner based on above description, interoperates the terms “directed” and “redirected” as “mapped” and “remapped” respectively. Therefore, the Examiner respectfully disagrees and asserts the reference of Iyer et al. (US 2018/0196710 A1) in paragraphs [0107] –[0109] teaches such limitation. For example, as noted above, a CRC syndrome can be included in each flit of data sent on an MCPL, regardless of data (or stream) type. Using the syndrome, individual bit errors can be identified and mapped to corresponding physical lanes assigned for use in the MCPL. After a threshold or statically significant amount of bit errors are identified for a particular physical lane, the logical PHY, a software management system, or other logic can determine that the particular lane is marginal. To avoid a system fault caused by this marginal lane, the MCPL can be reconfigured without bringing down the system. In one example, the logical assignment of lanes can be shifted away from the marginal lane toward a block of unused lanes in a data lane cluster used in the MCPL. This reconfiguration of the lanes can cause a re-routing of the lanes used in the MCPL and can include causing the MCPL to enter a link state that allows for the reconfiguring. See paragraph [0107].In one example, a modified re-centering link state and process can be enabled and a sideband lane can be used to communicate with the transmitting and receiving devices to orchestrate the reconfiguration. For instance, the software- or hardware-based lane manager can use the MCPL sideband to direct the remote transmitter to reconfigure the link to cause traffic of each lane to the left (or right) of the marginal lane to be rerouted its adjacent away from the marginal lane. The unused lane adopted by the reconfigured MCPL may be ready for data transmission as it has participated in the original centering performed during MCPL initialization (e.g., carrying a scrambled “0” value during the L0 state), allowing data to be immediately sent on the unused lane following reconfiguration. This can allow reconfiguration to forego recentering using a PRBS, among other efficiencies. In other instances, unused lanes can be kept idle during the L0 data transmitting state to save power. In these instances, a reconfiguration can be performed (again, without bringing down the link) but with a PRBS used in both the reconfiguration and recentering states. See paragraph [0108].
Reconfiguring a link to account for an identified marginal lane by re-routing a portion of the lanes to adjacent lanes (and one unused lane) can minimize the overall routing impact. A lane multiplexer of the transmitting and/or receiving devices rerouting can perform the rerouting. In some implementations, the lane multiplexer can be implemented in software or the logical PHY 630, while in other implementation the lane multiplexer can be implemented in hardware of the physical PHY 625. In some examples, the lane multiplexer can be merged into other multiplexers, such as loopback slave and lane reversal multiplexers in the logical PHY 630. In some instances, lane multiplexer can be advantageously implemented in software or the logical PHY 630 to avoid complications arising from other circuits, as well as control lane clusters (e.g., common cluster) at some data lanes cluster boundaries, among other example considerations. See paragraph [0109].
Also, the applicant contends that the office action fails to teach or suggest the limitation of "encoded information using a die-to-die system, wherein the encoded information comprises data and error correction information; decode the data and the error correction information from the encoded information." As recited in claim 9.
The Examiner respectfully disagrees and asserts the reference of Iyer et al. (US 2018/0196710 A1) in paragraph [0093] and Fig. 12 teaches such limitations. For example, turning to FIG. 12, a simplified block diagram 1200 is shown representing components implemented in hardware and/or software that can be provided, in some instances, to identify problem lanes from CRC syndrome values identified during CRC error calculations. For example, a first device 1205 can be coupled to a second device 1210 over an MCPL 1215. The first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215. (It should be appreciated that in other instances, device 1210 can send data as the transmitting device over a MCPL to device 1205, among other examples.) The first device 1205 can include logic 1220 to generate one or more flits for transmission across the MCPL 1215. A packet, message, or other formulation of data to be sent over the MCPL can comprise one or more flits. Each flit can include a CRC value calculated and encoded using a CRC generator 1225. The flits can be sent over the link 1215 to the second receiving device 1210. The second device 1210 can include logic to receive the flit and decode, or otherwise identify, the flit, including header values, slot values, and the CRC value (e.g., using CRC checking logic 1230). Also see Fig. 12 printed below for your convenience.
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Further, the applicant contends that the office action fails to teach or suggest the limitation of “correct an error in the data using the error correction information.” As recited in claim 9. The Examiner notes that the applicant’s arguments regarding the above limitations have been considered but are moot in view of the new ground(s) of rejection. In addition, the Examiner maintained the reference of over Iyer et al. (US 2018/0196710 A1) since there is no further argument/s regarding to this reference.
Furthermore, the applicant contends that the office action fails to teach or suggest the limitation of "perform a first send operation comprising sending the data and a first portion of the error correction information using a die-to-die system, wherein the first portion of the error correction information comprises partial error correction information." As recited in claim 12.
The Examiner respectfully disagrees and asserts the reference of Iyer et al. (US 2018/0196710 A1) in paragraphs [0048],[0091]-[0093] and Fig. 12 teaches such limitations. For example, Link layer 210, also referred to as data link layer 210, acts as an intermediate stage between transaction layer 205 and the physical layer 220. In one embodiment, a responsibility of the data link layer 210 is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device. See paragraph [0048].
In one implementation, MCPL logic can be provided that includes the capability of identifying specific marginal lanes and taking action, autonomously, to replace the marginal lane before a hard fault results without bringing the system down. Packets sent on a high speed link can be protected by checksum, parity, and other values that allow bit errors in the packet to be detected. In one example, at least some of the protocols sent on an MCPL link can be protected with by a CRC. For CRC, a particular corresponding packet is treated as a Galois Field polynomial (e.g., GF(2)), which is divided by the CRC polynomial. The remainder, or checksum, can then be appended to the packet before transmit. At the receiving end, the receiver can attempt to perform the same calculation. If no bit errors are present in the packet, the same operation will always yield a fixed remainder (or syndrome). Bits in error, however, would cause the syndrome to be different from the fixed one. See paragraph [0091].
In one particular example, a common CRC can be used in each of the types of data sent over an MCPL. For instance, a 16-bit CRC polynomial can be added to each of the flits, packets, or other data (of varying protocols) sent over an MCPL. In one example, the CRC polynomial can be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link. In one example, syndrome properties of a 0x1f053 16-bit polynomial calculation can be used to identify bad lanes. Such a CRC polynomial can possess capabilities that allow all 1, 2, 3 bit errors and almost all 4 bit errors on an MCPL flit to be identified. See paragraph [0092].
Turning to FIG. 12, a simplified block diagram 1200 is shown representing components implemented in hardware and/or software that can be provided, in some instances, to identify problem lanes from CRC syndrome values identified during CRC error calculations. For example, a first device 1205 can be coupled to a second device 1210 over an MCPL 1215. The first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215. (It should be appreciated that in other instances, device 1210 can send data as the transmitting device over a MCPL to device 1205, among other examples.) The first device 1205 can include logic 1220 to generate one or more flits for transmission across the MCPL 1215. A packet, message, or other formulation of data to be sent over the MCPL can comprise one or more flits. Each flit can include a CRC value calculated and encoded using a CRC generator 1225. The flits can be sent over the link 1215 to the second receiving device 1210. The second device 1210 can include logic to receive the flit and decode, or otherwise identify, the flit, including header values, slot values, and the CRC value (e.g., using CRC checking logic 1230). See paragraph [0093].
In addition, the applicant contends that the office action fails to teach or suggest the limitation of " wherein the first portion of the error correction information comprises partial error correction information." As recited in claim 12.
The Examiner respectfully disagrees and asserts the reference of Iyer et al. (US 2018/0196710 A1) in paragraph [0094] teaches such limitations. For example, A receiving device can utilize a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device can regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value with the received CRC value (e.g., using CRC checking logic 1230) to determine bit errors. An error checksum (or residue or “syndrome”) can be generated (e.g., using CRC checking logic 1230) during the comparison in response to an error in the flit (and a mismatch between the regenerated CRC value and received CRC value). In some cases, a syndrome can be generated during regeneration of the CRC on the payload portion of the flit at the receiving device and the regenerated CRC can be compared against the received CRC value, for instance, through a bit-wise XOR comparison, with the value resulting from the comparison embodying the syndrome. In another example, a CRC can be performed at the receiving device on the entire flit (i.e., including the received CRC field), with the result of this operation embodying the syndrome. The syndrome can be generated at the receiver using hardware or firmware, or alternatively, the syndrome can be generated by software, such as software supervising operation of the receiver and link, among other potential implementations. In one specific implementation, a 16-bit syndrome value can be generated when errors are detected from a 16-bit CRC value. Other implementations can use other error residue values.
Finally, the applicant contends that the office action fails to teach or suggest the limitation of "perform, based on the request, a second send operation comprising sending a second portion of the error correction information, wherein the second portion of the error correction information comprises additional partial error correction information." As recited in claim 12.
The Examiner notes that the applicant’s arguments regarding the above limitations have been considered but are moot in view of the new ground(s) of rejection. In addition, the Examiner maintained the reference of over Iyer et al. (US 2018/0196710 A1) since there is no further argument/s regarding to this reference.
Claim Objections
6. Claims 1 objected to because of the following informalities:
claim 1 recites the limitations of “receive a first byte directed to a first lane of two or more lanes of a die- to-die system; receive a second byte directed to a second lane of the two or more lanes of the die-to-die system; transmit, using one lane of the two or more lanes of the die-to-die system, a portion of the first byte; redirect a portion of the second byte to the one lane of the two or more lanes of the die-to-die system.” The terms “directed” and “redirected “ do not clearly been supported in the applicant’s specification in abstract and paragraph [0005] describes that "an apparatus may include a die including at least one circuit configured to receive a first byte mapped to a first lane of two or more lanes of a die-to-die system, receive a second byte mapped to a second lane of the two or more lanes of the die-to-die system, transmit,” and in paragraph [0091] describes that “In the interleaving scheme illustrated in FIG. 6, however, bytes from the byte mappers 611 may be input to an interleaving function 613 that may generate remapped bytes 614-0, 614-1, 614-2, and/or 614-3 having revised bitmaps as illustrated in FIG. 6. For example, bits 0 and 4 from byte mappers 611-0, 611-1, 611-2, and/or 611-3 may be combined in remapped byte 614-0. Similarly, bits 1 and 5 may be combined in remapped byte 614-1.” Therefore, the Examiner suggests that the terms “directed” and “redirected” be changed to “mapped” and “remapped”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-7 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer et al. (US 2018/0196710 A1) "herein after as Iyer ‘710" in view of Lanka et al. (2021/0004347 A1) "herein after as Lanka."
As per claim 1:
Iyer ‘710 substantially teaches or discloses an apparatus comprising (see Fig. 5): a die comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520): receive a first byte directed to a first lane of two or more lanes of a die-to-die system (see paragraph [0092], herein the CRC polynomial can be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link, and paragraph [0132], herein receive first data on a plurality of data lanes of a physical link, receive a stream signal corresponding to the first data on a stream lane identifying a type of the first data); receive a second byte directed to a second lane of the two or more lanes of the die-to-die system (see paragraph [0132], herein receive second data on at least a portion of the plurality of data lanes, receive a stream signal corresponding to the second data on the stream lane identifying a type of the second data); transmit, using one lane of the two or more lanes of the die-to-die system, a portion of the first byte (see paragraph [0051], herein an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received); redirect a portion of the second byte to the one lane of the two or more lanes of the die-to-die system (see paragraph [0108], herein the software- or hardware-based lane manager can use the MCPL sideband to direct the remote transmitter to reconfigure the link to cause traffic of each lane to the left (or right) of the marginal lane to be rerouted its adjacent away from the marginal lane, and paragraphs [1017] & [0107]).
Iyer ‘710 does not explicitly teach transmit, using the one lane of the two or more lanes of the die-to-die system, a portion of the second byte.
However, Lanka in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0115], herein which illustrates one or more operations for determining whether a second criterion is met in the other embodiment of an approximate majority vote based DBI technique. At 1322, majority vote logic is applied to a second set of bits (second bits) of a plurality of bits of original data to be transmitted in a new clock cycle; and paragraph [0188], herein the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710 with the teachings of Lanka by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
As per claim 2:
Iyer ‘710 teaches that wherein the one lane of the two or more lanes of the die-to-die system is the first lane of the two or more lanes of the die-to-die system (see paragraph [0069], herein data sent on each of the lanes of the MCPL can be strictly aligned to the strobe signal, and paragraph [0096], herein the bit-to-lane mapping module 1260 can determine the lanes used in the sending of a particular flit and thereby determine the bit ordering used during the transmission to determine the specific lane on which each flit bit was sent).
As per claim 3:
Iyer ‘710 teaches that wherein the one lane of the two or more lanes of the die-to-die system is a third lane of the two or more lanes of the die-to-die system (see paragraph [0069], herein data sent on each of the lanes of the MCPL can be strictly aligned to the strobe signal, and paragraph [0096], herein the bit-to-lane mapping module 1260 can determine the lanes used in the sending of a particular flit and thereby determine the bit ordering used during the transmission to determine the specific lane on which each flit bit was sent).
As per claim 4:
Iyer ‘710 teaches that wherein the portion of the first byte is a first portion of the first byte, the portion of the second byte is a first portion of the second byte, the one lane of the two or more lanes of the die-to-die system is a first one lane of the two or more lanes of the die-to-die system (see paragraph [0101], herein illustrated in FIG. 13C, an example bit mapping of link-to-link packets (e.g., LLP packets) sent over an example MCPL is shown. LLPs can be 4 bytes each and each LLP (e.g., LLP0, LLP1, LLP2, etc.) can be sent four consecutive times), and the at least one circuit is configured to: generate a third byte comprising a second portion of the first byte and a second portion of the second byte; and transmit, using a second one lane of the two or more lanes of the die-to-die system, the third byte (see paragraph [0093], herein The first device 1205 can include logic 1220 to generate one or more flits for transmission across the MCPL 1215. A packet, message, or other formulation of data to be sent over the MCPL can comprise one or more flits, and Fig. 12).
As per claim 5:
Iyer ‘710 teaches that wherein the second one lane of the two or more lanes of the die-to-die system is the second lane of the two or more lanes of the die-to-die system (see paragraph [0056], herein FIG. 5 is a simplified block diagram 500 illustrating an example multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520, and Fig. 5).
As per claim 6:
Iyer ‘710 teaches that wherein the second one lane of the two or more lanes of the die-to-die system is a third lane of the two or more lanes of the die-to-die system (see paragraph [0056], herein FIG. 5 is a simplified block diagram 500 illustrating an example multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520, and Fig. 5).
As per claim 7:
Iyer ‘710 teaches that wherein the at least one circuit is configured to: generate error correction information for the portion of the first byte and the portion of the second byte; and transmit, using a lane of the die-to-die system, at least a portion of the error correction information (see paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes, determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lane).
8. Claims 9 and 11 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer et al. (US 2018/0196710 A1) "herein after as Iyer ‘710" in view of Iyer et al. (2020/0244397 A1) "herein after as Iyer ‘397."
As per claim 9:
Iyer ‘710 substantially teaches or discloses an apparatus comprising: a die (see Figs. 5 and 12) comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520; and Fig. 12 transmitting device 105 & receive device 1210); receive encoded information using a die-to-die system, wherein the encoded information comprises data and error correction information (see paragraph [0093], the first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215 ---- Each flit can include a CRC value calculated and encoded using a CRC generator 1225. The flits can be sent over the link 1215 to the second receiving device 1210); decode the data and the error correction information from the encoded information (see paragraph [0093], herein The second device 1210 can include logic to receive the flit and decode, or otherwise identify, the flit, including header values, slot values, and the CRC value (e.g., using CRC checking logic 1230)); encode the data and the error correction information to generate encoded information (see paragraph [0069], herein the stream signal can be an encoded signal (e.g., 1 byte of data for a byte time period window; and paragraph [0093], herein Each flit can include a CRC value calculated and encoded using a CRC generator 1225); and transmit, using the die-to-die system, at least a portion of the encoded information (see paragraph [0069], herein that is encoded to identify the protocol that applies to data being sent during the same time period window); and paragraph [0093], herein the flits can be sent over the link 1215 to the second receiving device 1210).
Iyer ‘710 does not explicitly teach correct an error in the data using the error correction information.
However, Iyer ‘397 in the same the field of endeavor teaches correct an error in the data using the error correction information (see paragraph [0092], herein the code and parity values can be selected such that the receiving device can readily identify which bits of the stream ID code have errors and cause these bits to be flipped to correct the stream ID, for instance, using stream correction logic 1235 of the receiving device. The parity detection 1230 and stream correction 1235 can occur in advance of the corresponding data being processed at the receiving device 1215, allowing any bit errors present in the stream ID code to be identified and corrected such that the stream ID code (and its corresponding data) are properly processed at the receiver). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710 with the teachings of Iyer ‘397 by correcting an error in the data using the error correction information. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the correcting an error in the data using the error correction information would have increased error detection and correction capability.
As per claim 11:
Iyer ‘710 teaches that wherein the at least one circuit is configured to generate the error correction information using an error correction code (see paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes, determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lane).
9. Claims 12-13 and 20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer ‘710 in view in further view of Lee et al. (US 2022/0253244 A1) "herein after as Lee."
As per claim 12:
Iyer ‘710 substantially teaches or discloses an apparatus comprising (see Fig. 5): a die comprising at least one circuit configured to (see paragraph [0056], herein multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520): receive data (see paragraph [0092], herein the CRC polynomial can be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link, and paragraph [0132], herein receive first data on a plurality of data lanes of a physical link, receive a stream signal corresponding to the first data on a stream lane identifying a type of the first data); generate error correction information for the data (see paragraph [0094], herein a receiving device can utilize a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device can regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value with the received CRC value (e.g., using CRC checking logic 1230) to determine bit errors; paragraph [0146], herein determine a first error correction code for first data to be sent on a plurality of data lanes of a physical link, send the first data with the first error correction code on the plurality of data lanes); perform a first send operation comprising sending the data and a first portion of the error correction information using a die-to-die system, (see paragraph [0093], herein the first device 1205, in this example, can be a transmitting device in a particular transaction (or instance) and send data to the second, receiving device 1210 over the MCPL 1215. (It should be appreciated that in other instances, device 1210 can send data as the transmitting device over a MCPL to device 1205) wherein the first portion of the error correction information comprises partial error correction information (see paragraph [0094], herein A receiving device can utilize a CRC value in a received flit to identify bit errors in the flit. In some implementations, the receiving device can regenerate the CRC from the remaining bits of the received flits and compare the regenerated CRC value with the received CRC value (e.g., using CRC checking logic 1230) to determine bit errors. An error checksum (or residue or “syndrome”) can be generated (e.g., using CRC checking logic 1230) during the comparison in response to an error in the flit (and a mismatch between the regenerated CRC value and received CRC value); receive, based on the first send operation, a request (see paragraph [0098], herein Upon determining that one or more lanes of a link are experiencing problems, based on statistically significant numbers of bit errors determined for the lane from syndrome values 1240 and/or checksum comparison values 1280, a lane manager 1270 can be invoked to perform actions on the lane(s) or instruct one or both of the devices 1205, 1210 to enter a reconfiguration state to correct the issue). Iyer ‘710 does not explicitly teach perform, based on the request, a second send operation comprising sending a second portion of the error correction information, wherein the second portion of the error correction information comprises additional partial error correction information.
However, Lee in the same the field of endeavor teaches perform, based on the request, a second send operation comprising sending a second portion of the error correction information, wherein the second portion of the error correction information comprises additional partial error correction information (see paragraph [0015], herein the journal data may include first page data and second page data, the first page data may include first partial data and first parity data, and the second page data may include second partial data and second parity data. The first parity data may be generated based on the first partial data, and the second parity data may be generated based on the first partial data and the second partial data). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710 with the teachings of Lee by perform a second send operation comprising sending a second portion of the error correction information, wherein the second portion of the error correction information comprises additional partial error correction information.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the perform a second send operation comprising sending a second portion of the error correction information, wherein the second portion of the error correction information comprises additional partial error correction information would have improved the error detection and correction capability.
As per claim 13:
Iyer ‘710 teaches the request is a first request, and the at least one circuit is further configured to: receive, based on the second send operation, a second request (see paragraph [0146], herein determine a second error correction code for the second data to be sent on at least a portion of the data lanes of the physical link, and send the second data with the second error correction code on at least the portion of the data lanes. The first and second data can be data of different types or protocols. The first error correction code and the second error correction code can each be instances of a same error correction code type).
Iyer ‘710 does not explicitly teach and perform, based on the second request, a third send operation comprising sending a third portion of the error correction information.
However, Lee in the same the field of endeavor teaches and perform, based on the second request, a third send operation comprising sending a third portion of the error correction information (see paragraph [0119], herein the first page data PG1 may be generated by adding the first parity data PT1 to the first partial data PD1 including the first user data UD1 and the first meta data MD1, and the second page data PG2 may be generated by adding the second parity data PT2 to the second partial data PD2 including the second user data UD2 and the second meta data MD2. In addition, the third page data PG3 may be generated by adding the third parity data PT3 to the third partial data PD3 including the third user data UD3 and the third meta data MD3). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710 with the teachings of Lee by and perform a third send operation comprising sending a third portion of the error correction information.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the and perform a third send operation comprising sending a third portion of the error correction information would have improved the error detection and correction capability.
As per claim 20:
Iyer ‘710 teaches that wherein the at least one circuit comprises a buffer configured to store at least a portion of the error correction information (see Fig. 12, CRC generator 1225).
10. Claim 8 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer ‘710 in view of Lanka and in further view of Pan et al. (US 2019/0190655 A1) "herein after as Pan."
As per claim 8:
Iyer ‘710-Lanka as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using variable rate coding.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Lanka as combined with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
11. Claim 10 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer et al. (US 2018/0196710 A1) "herein after as Iyer ‘710" in view of Iyer et al. (2020/0244397 A1) "herein after as Iyer ‘397" in further view of Pan et al. (US 2019/0190655 A1)"herein after as Pan."
As per claim 10:
Iyer ‘710-Iyer ‘397 as combined does not explicitly teach wherein the at least one circuit is configured to configured to generate the error correction information using variable rate coding.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Iyer ‘397 as combined with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
12. Claims 15-19 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Iyer ‘710 in view of Lee and in further view of Pan et al. (US 2019/0190655 A1) "herein after as Pan."
As per claim 15:
Iyer ‘710 -Lee as combined does not explicitly teach determine the first portion of the error correction information based on a coding rate.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to determine the first portion of the error correction information based on a coding rate (see paragraph [0007], herein the WTRU may determine the performance and/or latency requirements based on a capability of a decoder, an information block size, and/or a coding rate and paragraph [0095]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Lee as combined with the teachings of Pan by determining the first portion of the error correction information based on a coding rate. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the determining the first portion of the error correction information based on a coding rate would have improved error correction capability.
As per claim 16:
Iyer ‘710 -Lee as combined does not explicitly wherein the at least one circuit is configured to generate the error correction information using variable rate coding. However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using variable rate coding (see paragraph [0135], herein Some variable rates encoding of high priority control information may be applied, e.g., in addition to error check bits added to WTRU feedback). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710 -Lee as combined with the teachings of Pan by generating the error correction information using variable rate coding. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using variable rate coding would have improved error correction capability.
As per claim 17:
Iyer ‘710 -Lee as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using a convolutional code.
However, Pan in the same the field of endeavor teaches to generate the error correction information using a convolutional code (see paragraph [0110], herein Polar coding may outperform other coding schemes such as convolutional codes (e.g., Tail-Biting CC (TBCC) and/or Trellis-Termination CC (TTCC)), LDPC, and/or Turbo codes at small payload sizes (e.g., 20 bits or 40 bits). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Lee as combined with the teachings of Pan by to generating the error correction information using a convolutional code. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using a convolutional code would have improved error correction capability.
As per claim 18:
Iyer ‘710-Lee as combined does not explicitly teach wherein the at least one circuit is configured to generate the error correction information using a turbo code.
However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to generate the error correction information using a turbo code (see paragraph (see paragraph [0110], herein Polar coding may outperform other coding schemes such as convolutional codes (e.g., Tail-Biting CC (TBCC) and/or Trellis-Termination CC (TTCC)), LDPC, and/or Turbo codes at small payload sizes (e.g., 20 bits or 40 bits). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Lee as combined with the teachings of Pan by generating the error correction information using a turbo code. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the error correction information using a turbo code would have improved error correction capability.
As per claim 19:
Iyer ‘710-Lee as combined does not explicitly teach wherein the at least one circuit is configured to determine the portion of the error correction information based on a coding rate. However, Pan in the same the field of endeavor teaches wherein the at least one circuit is configured to determine the first portion of the error correction information based on a coding rate (see paragraph [0007], herein the WTRU may determine the performance and/or latency requirements based on a capability of a decoder, an information block size, and/or a coding rate and paragraph [0095]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Iyer ‘710-Lee as combined with the teachings of Pan by determining the first portion of the error correction information based on a coding rate. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the determining the first portion of the error correction information based on a coding rate would have improved error correction capability.
Examiner Notes
13. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
14. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
15. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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