DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4 and 13-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zlotnik et al. (US 20240322675).
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With respect to claim 1, fig. 2A of Zlotnik et al. (US 20240322675) discloses a semiconductor device comprising: a first regulator (221-1) configured to generate a first internal voltage (223-1); a logic circuit (230-1) configured to operate using the first internal voltage (223-1), and determine an operation mode ([0053], “The logic in the first voltage domain 220 can cause the data having the uncorrectable error to be reprocessed (“RE-PROCESS”) and to be communicated”); and a first transmission circuit (238-1) configured to transmit, using the first internal voltage (223-1 via logic 2369-6), an exit command (RE-PROCESS) of the first operation mode externally input as a first control signal during the first operation mode to the logic circuit (230-1) as an internal exit command (RE-PROCESS).
With respect to claim 2, Zlotnik et al. discloses the semiconductor device of claim 1, wherein the first operation mode (RE-PROCES mode) is an operation mode in which power consumption is minimized (see [0054], “That is, for at least some types of data reprocessing of the data responsive to detection of an error may utilize less power and/or have less computation overhead than performance of error correction..”), among a plurality of operation modes (uncorrectable error mode) of the semiconductor device.
With respect to claim 4, fig. 2A of Zlotnik et al. (US 20240322675) discloses the semiconductor device of claim 3, wherein the first transmission circuit (238-1) comprises at least one first level shifter (disclosed in figure 2A as 238-1 LS meaning level shifter) configured to shift a voltage level of the exit command using the first internal voltage (223-1 via logic 2369-6) to output the internal exit command (RE-PROCESS).
With respect to claim 13, fig. 2A of Zlotnik et al. (US 20240322675) discloses a semiconductor device comprising: a first regulator (221-1) configured to generate a first internal voltage (223-1); a second regulator (221-R) configured to generate a second internal voltage (223-X); a logic circuit configured (230-1) to operate using the first internal voltage (223-1), and turn off the second regulator (221-R) in a first operation mode; and a transmission circuit (238-S configured to transmit, using the second internal voltage (223-X), a control signal (from 135 output to control the voltage regulators) externally input during a second operation mode to the logic circuit (238-S) as a logic control signal.
With respect to claim 14, fig. 2A of Zlotnik et al. (US 20240322675) produces an operating method of a semiconductor device, the operating method comprising: transmitting a command instructing entry into a first operation mode to a logic circuit (220 having logic devices 230-1 and 230-2) through a first path (upper path using 223-1); entering, by the logic circuit (220 having logic devices 230-1 and 230-2) , the first operation mode in response to the command (command from controller from 135 in fig. 1); and transmitting an exit command (RE-PROCESS) of the first operation mode through a second path (lower path using 223-X) to the logic circuit (220 having logic devices 230-1 and 230-2).
With respect to claim 15, fig. 2A of Zlotnik et al. (US 20240322675) produces the operating method of claim 14, wherein transmitting the command through the first path comprises shifting a voltage level (shifting via level shifter 238-1) of the command (RE-PROCESS) using an internal voltage supplied (223-1) to the first path.
With respect to claim 16, fig. 2A of Zlotnik et al. (US 20240322675) produces the operating method of claim 14, wherein entering the first operation mode comprises turning off, by the logic circuit (220 having logic devices 230-1 and 230-2), a regulator (221-1) configured to supply an internal voltage (223-1) to the first path using an external voltage (external voltage from 135 controlling the main voltage regulator 221-1).
With respect to claim 17, fig. 2A of Zlotnik et al. (US 20240322675) produces the operating method of claim 14, wherein entering the first operation mode comprises enabling a first operation mode signal , by the logic circuit (220 having logic devices 230-1 and 230-2), to enable the second path (second path through 229-4.. etc.).
With respect to claim 18, fig. 2A of Zlotnik et al. (US 20240322675) produces an 18. The operating method of claim 14, wherein transmitting the exit command (RE-PROCESS) comprises shifting a voltage level of the exit command (RE-PROCESS) using an internal voltage supplied (223-X) to the second path (second path through 229-4.. etc.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3,5-6, 11-12 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zlotnik et al. (US 20240322675) in view of Linday (US 20130154104).
With respect to claim 3, Zlotnik et al. (US 20240322675) discloses the semiconductor device of claim 1, but fails to disclose further comprising at least one first pad configured to externally receive the first control signal.
It is well known in the art to connect components of memory systems with pads. For example, Linday (US 20130154104) teaches (See [0003], “In some applications, these internal lines may be connected to conductive pads, e.g., sometimes called "landing" pads, of the memory device, such as conductive pads mounted on a memory chip (e.g., memory die). For example, the conductive pads may be connected to pins or other conductive pads on a printed circuit board that forms a portion of a memory package.”
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teachings of Lindsay, to connect the components of Zlotnik via pads for the purpose of coupling components together. (First pad would be a pad connecting the main voltage regulator to receive control signal from 135 of fig. 1)
With respect to claim 5, fig. 2A of Zlotnik et al. (US 20240322675) discloses the semiconductor device of claim 4, wherein the logic circuit (230-1) is configured to generate a first operation mode signal (RE-PROCESS signal) that is enabled in the first operation mode (RE-PROCESS), and wherein the first transmission circuit (238-1) further comprises at least one first switch (230-3 would be the at least one switch) configured to electrically connect the at least one first pad (First pad would be a pad connecting the main voltage regulator to receive control signal from 135 of fig. 1) and the at least one first level shifter (238-1) in response to the first operation mode signal (RE-PROCESS signal).
With respect to claim 6, the combination above produces the semiconductor device of claim 3, further comprising: a second regulator (221-R) configured to generate a second internal voltage (223-X); and a second transmission circuit (238-S) configured to transmit, using the second internal voltage (223-X via 231), a second control signal (control signals from 135 of figure 1 for the second voltage regulator 221-R) externally input as a logic control signal (controlling a second logic circuit 225) during the second operation mode to the logic circuit (logic circuit 220).
With respect to claim 7, the combination above produces the semiconductor device of claim 6, but fails to disclose further comprising at least one second pad configured to externally receive the second control signal.
It is well known in the art to connect components of memory systems with pads. For example, Linday (US 20130154104) teaches (See [0003], “In some applications, these internal lines may be connected to conductive pads, e.g., sometimes called "landing" pads, of the memory device, such as conductive pads mounted on a memory chip (e.g., memory die). For example, the conductive pads may be connected to pins or other conductive pads on a printed circuit board that forms a portion of a memory package.”
Here, the combination above teaches the use of pads to connect circuits together, thus by extension it would be obvious for a first conductive pad to connect components of the first control signal and a second conductive pad to connect the signal for the second control signal. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teachings of Lindsay, to connect the components of Zlotnik via a second conductive pad input to receive the second control signal for the purpose of coupling components together.
With respect to claim 8, the combination above produces the semiconductor device of claim 7, wherein the second transmission circuit (238-S) comprises: at least one second level shifter (238-S is labelled as a level shifter) configured to shift a voltage level of the second control signal ( via 225) using the second internal voltage (223-X) to output a second internal control signal (UNCORRECTABLE ERROR AND/or Quantity OF CORRECTABLE ERRORS processing command); and a pass circuit (236, low pass filter) configured to output (Output to the second voltage regulator), using the second internal voltage (223-X controlling 231), the second internal control signal (UNCORRECTABLE ERROR or Quantity OF CORRECTABLE ERRORS processing command)) received from the second level shifter as the logic control signal (Controlling 220).
With respect to claim 11, the combination above produces the semiconductor device of claim 6, wherein the second control signal (control signal to Secondary votlage regulator 221-R from fig. 1 135) comprises a command instructing entry into the first operation mode (RE-PROCESS).
With respect to claim 12, the combination above produces the semiconductor device of
6, wherein the second operation mode (UNCORRECTABLE ERROR) is not an operation mode that consumes the least power among a plurality of operation modes (First operation mode consumes the least amount of power. See [0054], “That is, for at least some types of data reprocessing of the data responsive to detection of an error may utilize less power and/or have less computation overhead than performance of error correction..”), of the semiconductor device.
With respect to claim 19, fig. 2A of Zlotnik et al. (US 20240322675) produces the operating method of claim 14, wherein an internal voltage (223-R) but fails to disclose wherein the internal voltage used in the first path is lower than an internal voltage used in the second path.
Zlotnik does discloses wherein the internal voltage used in the first path is higher than the voltage in the second path (see [0054], “That is, for at least some types of data reprocessing of the data responsive to detection of an error may utilize less power and/or have less computation overhead than performance of error correction..”) (See also [0071]; “.In some embodiments, the first supply voltage may be higher than the second supply voltage, as described herein. For instance, the first supply voltage may be substantially equal to a nominal voltage (e.g., a nominal voltage of the first voltage regulator) and the second supply voltage substantially equal to a value that is less than the nominal voltage” and [0059]).
It whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to reverse the paths such that the first path is lower and the second path is higher such that the voltage in the upper path is a lower negative voltage. As this is seen as mere reversal of parts. See In re Gazda, 219 F.2d 449, 104 USPQ 400 (CCPA 1955) (Prior art disclosed a clock fixed to the stationary steering wheel column of an automobile while the gear for winding the clock moves with steering wheel; mere reversal of such movement, so the clock moves with wheel, was held to be an obvious modification.). (Note: Furthermore, the first path may be seen as the path through the altered supply voltage and the second path as the path through the second regulator which also would produce the claimed limitation. )
With respect to claim 20, fig. 2A of Zlotnik et al. (US 20240322675) produces the operating method of claim 14, but fails to disclose further comprising: externally receiving the command through a first pad (PAD connecting 221-1); and externally receiving the exit command (RE-PROCESS).through a second pad (pad connecting to LOGiC) which is different from the first pad.
It is well known in the art to connect components of memory systems with pads. For example, Linday (US 20130154104) teaches (See [0003], “In some applications, these internal lines may be connected to conductive pads, e.g., sometimes called "landing" pads, of the memory device, such as conductive pads mounted on a memory chip (e.g., memory die). For example, the conductive pads may be connected to pins or other conductive pads on a printed circuit board that forms a portion of a memory package.”
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teachings of Lindsay, to connect the components of Zlotnik via pads for the purpose of coupling components together.
Allowable Subject Matter
Claims 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 9, the prior art of record fails to suggest or disclose the semiconductor device of claim 8, wherein the second transmission circuit further comprises at least one third level shifter configured to shift a voltage level of the first control signal using the second internal voltage to output a first internal control signal to the pass circuit.
Here, no third level shifter is present as required.
With respect to claim 10, the prior art of record fails to suggest or disclose the semiconductor device of claim 9, wherein the logic circuit is configured to generate a second operation mode signal that is enabled in the second operation mode, and wherein the second transmission circuit further comprises at least one second switch configured to electrically connect the at least one first pad and the at least one third level shifter in response to the second operation mode signal.
Here, no third level shifter is present as required.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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/KHAREEM E ALMO/Examiner, Art Unit 2849