DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2017/0110056; hereinafter Hu ‘056), in view of Hu et al (US 2015/0187269; hereinafter Hu ‘269).
• Regarding claim 1, Hu ‘056 discloses a pixel circuit (figure 2), comprising:
a light emitting element, having an anode and a cathode receiving a supply voltage (element L in figure 2 and ¶ 76);
a first transistor (element T3 in figure 2 and ¶s 79-81), having a first terminal receiving an operating high voltage (ELVdd in figure 2), a control terminal receiving a scan signal (S2 in figure 2; where S2 is at least functionally equivalent to Vscan in figures 2 and 3), and a second terminal coupled to the cathode of the light emitting element (note the relationship between elements L and T3 in figure 2);
a capacitor, having a first terminal and a second terminal (element C in figure 2 and ¶s 79-81);
a driving circuit (element T2 in figure 2 and ¶s 79-81), coupled between the cathode of the light emitting element and the second terminal of the capacitor (note the relationship between elements C, L, and T2 in figure 2) and receiving a driving voltage to provide a driving current based on the driving voltage (¶ 85);
a light emitting control circuit (element T1 in figure 2 and ¶s 79-81), coupled between the driving circuit and a ground voltage (note the relationship between ELVss and elements T1 and T2 in figure 2), and receiving a light emitting signal (S1 in figure 2 and ¶ 95);
a reset circuit (element T5 in figure 2 and ¶s 79-81), coupled between a reference voltage and the driving voltage (note the relationship between Vref and elements T2 and T5 in figure 2), and receiving the scan signal (Vscan in figure 2; where Vscan is at least functionally equivalent to S2 in figures 2 and 3);
a voltage dividing circuit (element T6 in figure 2 and ¶s 79-81), coupled between the driving voltage and the first terminal of the capacitor (note the relationship between elements C, T2, and T6 in figure 21), and receiving a light emitting signal (S3 in figure 2; where S3 is at least functionally equivalent to S1 in figures 2 and 3); and
a data input circuit (element T4 in figure 2 and ¶s 79-81), coupled between the first terminal of the capacitor and a data input signal (note the relationship between Vdata and elemnts C and T4 in figure 2), and receiving the scan signal (Vscan in figure 2).
However, Hu ‘056 fails to disclose the additional details of the pixel circuit.
In the same field of endeavor, Hu ‘269 discloses where a voltage cvalue of the operating high voltage is higher than the supply voltage (V1 in figure 6 and ¶ 34).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hu ‘056 according to the teachings of Hu ‘269, for the purpose of turning off an OLED during a data signal loading phase (¶ 51).
• Regarding claims 2-7 and 10, Hu ‘056, in view of Hu ‘269, discloses everything claimed, as applied to claim 1. Additionally, Hu ‘056 discloses where:
Claim 2: the reset circuit comprises:
a second transistor (element T5 in figure 2 and ¶s 79-81), having
a first terminal receiving the reference voltage (Vref in figure 2),
a control terminal receiving the scan signal (Vscan in figure 2), and
a second terminal coupled to the driving voltage (note the relationship between elements T2 and T5 in figure 2).
Claim 3: the voltage dividing circuit comprises:
a third transistor (element T6 in figure 2 and ¶s 79-81), having
a first terminal coupled to the driving voltage (note the relationship between elements T2 and T6 in figure 2),
a control terminal receiving the light emitting signal (S3 in figure 2), and
a second terminal coupled to the first terminal of the capacitor (note the relationship between elements C and T6 in figure 2).
Claim 4: the data input circuit comprises:
a fourth transistor (element T4 in figure 2 and ¶s 79-81), having
a first terminal coupled to the first terminal of the capacitor (note the relationship between elements C and T4 in figure 2),
a control terminal receiving the scan signal (Vscan in figure 2), and
a second terminal coupled to the data input signal (Vdata in figure 2).
Claim 5: the driving circuit comprises:
a fifth transistor (element T2 in figure 2 and ¶s 79-81), having
a first terminal coupled to the cathode of the light emitting element (note the relationship between elements L and T2 in figure 2),
a control terminal receiving the driving voltage (node c in figure 2 and ¶s 85, 90, and 95), and
a second terminal coupled to the second terminal of the capacitor (note the relationship between elements C and T2 in figure 2).
Claim 6: the light emitting control circuit comprises:
a sixth transistor (element T1 in figure 2 and ¶s 79-81), having
a first terminal coupled to the second terminal of the capacitor (note the relationship between elements C and T1 in figure 2),
a control terminal receiving the light emitting signal (S1 in figure 2), and
a second terminal receiving the ground voltage (ELVss in figure 2).
Claim 7: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all N-type transistors (¶ 68).
Claim 10: the light emitting element is a micro light emitting diode (at least suggested by “LED” in ¶s 76 and 127).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hu ‘056, in view of Hu ‘269, and further in view of Wu (US 2023/0116711).
• Regarding claims 8 and 9, Hu ‘056, in view of Hu ‘269, discloses everything claimed, as applied to claim 1. However, Hu ‘056, in view of Hu ‘269, fails to disclose the additional details of the pixel circuit.
In the same field of endeavor, Wu discloses where:
Claim 8: the pixel circuit according further comprises:
a test circuit (elements 102 and 104 in figure 2 and ¶s 30 and 31; where applicant does not define a “test circuit” as anything more than a pair of transistors which transmit a voltage to a node of a pixel (see ¶s 40-43 of the specification, as filed)), coupled to the second terminal of the capacitor (note the relationship between elements 101, 104, and T6 in figure 2; where claims 5 and 6 of the instant application indicate that the fifth and sixth transistors are also connected to the second terminal of the capacitor, thus making the arrangement of figure 2 of Wu equivalent to the claimed invention) and receiving the scan signal, a test activation signal, and a test data signal to transmit the test data signal to the second terminal of the capacitor based on the scan signal and the test activation signal (Sn, Sn-1, and Vref1, respectively, in figure 2 and ¶ 31; where, due to the timing of Sn an dSn-1, Vref can be transmitted to the node formed between elements 101/T3, 104/T4, and T6).
Claim 9: the test circuit comprises:
a seventh transistor (element 104/T4 in figure 4 and ¶s 30 and 31), having a first terminal coupled to the second terminal of the capacitor (note the relationship between elements 101/T3, 104/T4, and T6 in figure 2, as previously explained), a control terminal receiving the scan signal (Sn in figure 2), and a second terminal (note the relationship between elements 102/T5 and 104/T4 in figure 2); and
an eighth transistor (element 102/T5 in figure 2 and ¶s 30 and 31), having a first terminal coupled to the second terminal of the seventh transistor (note the relationship between elements 102/T5 and 104/T4 in figure 2), a control terminal receiving the test activation signal (Sn-1 in figure 2), and a second terminal receiving the test data signal (Vref1 in figure 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hu ‘056, as modified by Hu ‘269, according to the teachings of Wu, for the purpose of clearing residual charges of the previous frame of image so as to improve the display effect of the display panel (¶ 31).
Claim 10 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Hu ‘056, in view of Hu ‘269, and further in view of Sakariya et al (US 2015/0348504; hereinafter Sakariya).
• Regarding claim 10, Hu ‘056, in view of Hu ‘269, discloses everything claimed, as applied to claim 1. However, Hu ‘056, in view of Hu ‘269, does not explicitly disclose where element L in figure 2 is a “micro” light emitting diode.
In the same field of endeavor, Sakariya discloses where the light emitting element is a micro light emitting diode (¶ 35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hu ‘056, as modified by Hu ‘269, according to the teachings of Sakariya, for the purpose of achieving achieve high resolutions, pixel densities, and subpixel densities in a display panel (¶ 35).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Closing Remarks/Comments
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622