DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants’ arguments, filed 7/6/26, with respect to the restriction of claims 18-20 have been fully considered and are persuasive. The restriction of claim 18-20 has been withdrawn. 14-17 remain restricted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li 20200089784 herein Li in view of Garcia et al 20190042111 herein Garcia.
Per claim 1, Li discloses: a controller configured to perform a compression operation on data received from outside of the memory expander to generate compressed data (fig. 1B, ¶0040; During communication, CPU 124 can send original data 172 (i.e., the uncompressed data which is to be subsequently compressed and written to a non-volatile storage) from DRAM DIMM 126 via a PCIe bus 192 to SSD 140. Upon receiving original data 172, SSD controller 142 can place data 172 in its internal DRAM buffer (i.e., a buffer 156 of DRAM 154). SSD controller 142 can, by a microprocessor 152, access original data 172 in buffer 156 and execute compression on original data 172 (compress 174 function, to obtain compressed data 182),) and generate mapping data including a device physical address for the compressed data; (fig. 1B, ¶0040; and can also determine and update the metadata associated with the compressed data (update metadata 176 function, to obtain metadata 178).) and a first memory device including a volatile memory that is connected to the controller through a first channel(fig. 1B, SSD 140 including DRAM and controller).
Li discloses storing the compressed data and generating the metadata in the DRAM but does not explicitly teach storing the metadata in the DRAM: a first mapping data region where the mapping data is stored and a first compressed data region where the compressed data is stored.
However, Garcia discloses: a first mapping data region where the mapping data is stored and a first compressed data region where the compressed data is stored (¶0037; The Metadata logic 144 includes H2S and FSI rebuilder logic 204 to rebuild the Host-SSD LBA (H2S) Mapping table 130 and the free space information table (FSI) 212 and meta marker/parser logic 210 to generate the metadata to be stored with the compressed data in the SSD 118 and to parse the stored metadata to rebuild the tables after an unexpected power loss.).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Li and Garcias compressed data and metadata management to ensure data is recoverable in the event of a failure (¶0021).
Per claim 2, Li discloses: the volatile memory is a dynamic random-access memory (DRAM) (fig. 1B, SSD 140 including DRAM and controller).
Per claim 18, Li discloses: generating compressed data and mapping data including a host physical address, in response to a compression request for data from the processor; (fig. 1B, ¶0040; During communication, CPU 124 can send original data 172 (i.e., the uncompressed data which is to be subsequently compressed and written to a non-volatile storage) from DRAM DIMM 126 via a PCIe bus 192 to SSD 140. Upon receiving original data 172, SSD controller 142 can place data 172 in its internal DRAM buffer (i.e., a buffer 156 of DRAM 154). SSD controller 142 can, by a microprocessor 152, access original data 172 in buffer 156 and execute compression on original data 172 (compress 174 function, to obtain compressed data 182),) (fig. 1B, ¶0040; and can also determine and update the metadata associated with the compressed data (update metadata 176 function, to obtain metadata 178).)
Li discloses storing the compressed data and generating the metadata in the DRAM but does not explicitly teach storing the metadata in the DRAM: providing a confirmation request requesting memory capacity information to a memory expander including a dynamic random-access memory (DRAM): providing memory capacity information corresponding to a first region, which is part of a memory device included in the memory expander, to a processor in response to the confirmation request; allocating a compressed data region and an uncompressed data region within the first region; and performing a write operation on the compressed data in the compressed data region and performing a write operation on the mapping data in a second region different from the first region within the memory device;
However, Garcia discloses: providing a confirmation request requesting memory capacity information to a memory expander including a dynamic random-access memory (DRAM): providing memory capacity information corresponding to a first region, which is part of a memory device included in the memory expander, to a processor in response to the confirmation request; allocating a compressed data region and an uncompressed data region within the first region; (¶0036; Compressed Space Management and Dynamic Capacity Logic (CSM DCL) 208 to manage compression/decompression operations; ) and performing a write operation on the compressed data in the compressed data region and performing a write operation on the mapping data in a second region different from the first region within the memory device (¶0037; The Metadata logic 144 includes H2S and FSI rebuilder logic 204 to rebuild the Host-SSD LBA (H2S) Mapping table 130 and the free space information table (FSI) 212 and meta marker/parser logic 210 to generate the metadata to be stored with the compressed data in the SSD 118 and to parse the stored metadata to rebuild the tables after an unexpected power loss.).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Li and Garcias compressed data and metadata management to ensure data is recoverable in the event of a failure (¶0021).
Per claim 19, Li discloses: the memory expander further includes a controller configured to generate the compressed data and the mapping data, and the memory device is configured to receive the compressed data and the mapping data through a first channel (fig. 1B, ¶0040; During communication, CPU 124 can send original data 172 (i.e., the uncompressed data which is to be subsequently compressed and written to a non-volatile storage) from DRAM DIMM 126 via a PCIe bus 192 to SSD 140. Upon receiving original data 172, SSD controller 142 can place data 172 in its internal DRAM buffer (i.e., a buffer 156 of DRAM 154). SSD controller 142 can, by a microprocessor 152, access original data 172 in buffer 156 and execute compression on original data 172 (compress 174 function, to obtain compressed data 182)).
Per claim 20, Garcia discloses: the compressed data includes first compressed data and second compressed data that are different from each other, the mapping data includes first mapping data for the first compressed data and second mapping data for the second compressed data, the memory expander further includes a controller configured to generate the first and second compressed data and the first and second mapping data, and the memory device includes a first memory device configured to receive the first compressed data and the second mapping data through a first channel, and a second memory device configured to receive the second compressed data and the first mapping data through a second channel different from the first channel (fig. 4A-B, ¶0043; In an embodiment, the metadata has 8 bytes (64 bits) to store a 32 bit Host LBA in the Host LBA field 314, a 3-bit number of sectors indicating the number of sectors (0-8) that store the compressed data for the host LBA in the Size field 316 and a 29 bit timestamp to store in the timestamp field 318; ¶0046; A H2S entry 400 is added to the H2S Mapping table each time an I/O Request to write one or more consecutive sectors in the SSD 118 is received from the I/O manager 206. A number assigned to the I/O Request is stored in the I/O request number 402 field in the H2S entry 400. A host logical block address identifying the first host block address of the I/O request is stored in a host block address 404 field of the H2S entry 400. A storage device logical block address (LBA) corresponding to the host block address is stored in the storage device LBA 302 field in the H2S entry 400. The number of compressed sectors field 408 stores the number sectors of compressed data ;the examiner notes that the limitation is merely claiming one or compressed and its corresponding metada).
Claim(s) 3-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li 20200089784 herein Li and Garcia et al 20190042111 herein Garcia in view of Choi et al 20240231615 herein Choi.
Per claim 3, Li discloses a PCIe interface but does not explicitly disclose: the controller includes a Compute eXpress Link (CXL) interface configured to receive the data
However, Choi discloses: the controller includes a Compute eXpress Link (CXL) interface configured to receive the data (¶0076; the CXL device 110 may include a Host-managed Device Memory (HDM) decoder or a Private Device Memory (PDM) decoder. The Host-Managed Device Memory (HDM) is a type of device-attached memory that can be mapped into a system-coherent address space and accessible to a host using a standard post-entry semantic scheme. The memory areas included in the CXL device 110 can be mapped through an HDM decoder.).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Li, Garcia and Choi’s memory expander to to overcome resource limitations. Choi improves the performance of the shared memory device (¶0020).
Per claim 4, Choi discloses: the CXL interface includes a host-managed device memory (HDM) decoder configured to map a host physical address received from outside of the memory expander and a memory region of the volatile memory, and the controller is configured to access the first compressed data region through the HDM decoder (¶0076; the CXL device 110 may include a Host-managed Device Memory (HDM) decoder or a Private Device Memory (PDM) decoder. The Host-Managed Device Memory (HDM) is a type of device-attached memory that can be mapped into a system-coherent address space and accessible to a host using a standard post-entry semantic scheme. The memory areas included in the CXL device 110 can be mapped through an HDM decoder.)).
Per claim 5, Garcia discloses: the device physical address includes a bank address and a row address corresponding to the first compressed data region, and column start information and column end information in the row address, and a size of the mapping data is 8 bytes or 16 bytes (fig. 4A-B, ¶0043; In an embodiment, the metadata has 8 bytes (64 bits) to store a 32 bit Host LBA in the Host LBA field 314, a 3-bit number of sectors indicating the number of sectors (0-8) that store the compressed data for the host LBA in the Size field 316 and a 29 bit timestamp to store in the timestamp field 318; ¶0046; A H2S entry 400 is added to the H2S Mapping table each time an I/O Request to write one or more consecutive sectors in the SSD 118 is received from the I/O manager 206. A number assigned to the I/O Request is stored in the I/O request number 402 field in the H2S entry 400. A host logical block address identifying the first host block address of the I/O request is stored in a host block address 404 field of the H2S entry 400. A storage device logical block address (LBA) corresponding to the host block address is stored in the storage device LBA 302 field in the H2S entry 400. The number of compressed sectors field 408 stores the number sectors of compressed data ;the examirer notes that the address in an SSD are organized in rows and columns).
Per claim 6, Garcia discloses: the data includes first and second data different from each other, the compressed data includes first compressed data for the first data and second compressed data for the second data, the mapping data includes first mapping data including a first device physical address of the first compressed data and second mapping data including a second device physical address of the second compressed data, and the first memory device is configured to read the first compressed data based on the first mapping data and read the second compressed data based on the second mapping data (fig. 4A-B, ¶0043; In an embodiment, the metadata has 8 bytes (64 bits) to store a 32 bit Host LBA in the Host LBA field 314, a 3-bit number of sectors indicating the number of sectors (0-8) that store the compressed data for the host LBA in the Size field 316 and a 29 bit timestamp to store in the timestamp field 318; ¶0046; A H2S entry 400 is added to the H2S Mapping table each time an I/O Request to write one or more consecutive sectors in the SSD 118 is received from the I/O manager 206. A number assigned to the I/O Request is stored in the I/O request number 402 field in the H2S entry 400. A host logical block address identifying the first host block address of the I/O request is stored in a host block address 404 field of the H2S entry 400. A storage device logical block address (LBA) corresponding to the host block address is stored in the storage device LBA 302 field in the H2S entry 400. The number of compressed sectors field 408 stores the number sectors of compressed data ;the examiner notes that the limitation is merely claiming one or compressed and its corresponding metada).
Per claim 7, Garcia discloses: the first memory device includes a plurality of banks that include a first and second bank different from each other, the mapping data is stored in at least a portion of the first bank, and the compressed data is stored in the plurality of banks other than the first bank (fig. 7A¶0037; The Metadata logic 144 includes H2S and FSI rebuilder logic 204 to rebuild the Host-SSD LBA (H2S) Mapping table 130 and the free space information table (FSI) 212 and meta marker/parser logic 210 to generate the metadata to be stored with the compressed data in the SSD 118 and to parse the stored metadata to rebuild the tables after an unexpected power loss; ¶0054; FIG. 6 is a flowgraph illustrating a restore operation to recover the mapping tables 146 (H2S mapping table 130 and FSI table 212) using the metadata 310 stored with each sector of compressed data in the SSD 118. The restore operation will be described for a SSD 118 in which 512 B of data (compressed data and pad (if required)) plus 8 B of metadata is stored in each SSD sector.).
Per claim 8, Garcia discloses: the first memory device is configured to provide the first compressed data and the second mapping data in an interleaving manner (¶0077; when connected to multiple host interfaces (e.g., the plurality of root ports), the Host-managed Device Memory (HDM) decoder or the Private Device Memory (PDM) decoder may support interleaving for memory areas).
Per claim 9, Garcia discloses: the first memory device includes a plurality of banks that include a first bank and a second bank different from each other, and the mapping data is stored in a predetermined row of each of the first bank and the second bank (¶0046; A H2S entry 400 is added to the H2S Mapping table each time an I/O Request to write one or more consecutive sectors in the SSD 118 is received from the I/O manager 206. A number assigned to the I/O Request is stored in the I/O request number 402 field in the H2S entry 400. A host logical block address identifying the first host block address of the I/O request is stored in a host block address 404 field of the H2S entry 400. A storage device logical block address (LBA) corresponding to the host block address is stored in the storage device LBA 302 field in the H2S entry 400. The number of compressed sectors field 408 stores the number sectors of compressed data; the examiner notes that the predetermined row is merely a mapped area of the compressed and metadata areas).
Per claim 10, Garcia discloses: the first and second mapping data are stored in the first bank, and the controller is configured such that when the first mapping data is read, the controller prefetches the second mapping data (¶0055-0056; fig. 7A-C; At block 600, 8 SSD sectors from the SSD. For example, contiguous sectors 702 numbered 0-7 shown in FIG. 7A are read starting with SSD LBA 0 and ending with SSD LBA 7. Processing continues with block 602. At block 602, the 8 B metadata stored with the 512 B compressed data for each of the 8 sectors is read. As described earlier, the metadata includes the Host LBA 314, size 316 and a timestamp 318. Processing continues with block 604).
Per claim 11, Choi discloses: a second memory device connected to the controller through a second channel different from the first channel and including a second mapping data region (fig. 4) where the mapping data is stored and a second compressed data region where the compressed data is stored, the first compressed data is stored in the first compressed data region, the second compressed data is stored in the second compressed data region, the second mapping data is stored in the first mapping data region, and the first mapping data is stored in the second mapping data region (fig. 4, ¶0080; The memory system 300 may correspond to the CXL device 110 described in FIG. 3. The memory system 300 may allocate, or release, the plurality of memory areas included in the plurality of memory devices 310A, 310B, 310C, . . . , 310Z in response to a request from the plurality of hosts 102A, 102B, 102C, . . . , 102N. According to an embodiment, at least some of the plurality of memory devices 310A, 310B, 310C, . . . , 310Z) can include plural memory areas allocated to at least two hosts 102A, 102B, 102C, . . . , 102N. For example, a first memory device 310A may include a plurality of memory areas allocated to two or more hosts (e.g., 102A, 102B, 102C, etc.). Operations or processes for allocating and releasing the plurality of memory areas will be described later with reference to FIGS. 6 to 8. The number of compressed sectors field 408 stores the number sectors of compressed data; the examiner notes that Choi discloses more than one logical devices).
Per claim 12, Li discloses: the data includes first and second data different from each other, the controller is configured to receive the first and second data to generate first compressed data for the first data, the first compressed data is stored in the first compressed data region, the first memory device further includes a first uncompressed data region where the second data is stored (fig. 5, ¶0043; the uncompressed data in the internal DRAM of the SSD. Thus, the uncompressed data is held physically inside the SSD, which is physically close to the NAND flash where the compressed data is to be stored. The uncompressed data is also physically close to the SSD controller, which has multiple microprocessors that may be used to perform compression. The SSD controller can access the data stored in its internal DRAM via the DRAM controller, such that after the data is successfully moved from the host to the SSD DRAM, one of the SSD microprocessors can execute a firmware program to compress the data. The SSD controller can then write the compressed data to the NAND flash. At the same time, the SSD controller can send metadata about the compressed file (e.g., “brief information” such as the length and the size of the compressed data) back to the host file systems).
Per claim 13, Li discloses: a size of the first data is 4KB, a size of the second data is 4KB, and a size of the first compressed data is 1KB (fig. 5, ¶0049; determine an amount of compression gain (ratio) (operation 516), and the operation continues at Label A of FIG. 5B. The compression gain can be expressed as a ratio of, e.g., a size of the compressed file to a size of the uncompressed file.; the examiner notes that the gain ratio is representative of any number represent a reduction in size of an uncompressed to compressed data.).
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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