Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mattina et al. (US Pat. No. 10606750), hereinafter referred to as Mattina.
As to claim 1, Mattina discloses a network packet (packet distribution engine, 940, Fig. 56; packet processing pipeline, 1000–1006, Fig. 57) processing apparatus comprising:
a packet buffer (incoming buffers and backing store, 1050, Fig. 60; memory interface and DMA buffers, 178, Fig. 14), arranged to store a network packet (incoming buffers and backing store for packets, 1050, Fig. 60);
a ring buffer (software virtualized command queue and hardware command queue, 708, 710, 712, Fig. 40A–40B), arranged to store a packet descriptor (descriptor in command queue, 720–724, Fig. 41A) of the network packet (incoming buffers and backing store for packets, 1050, Fig. 60), wherein the packet descriptor comprises a first field (descriptor metadata fields associated with buffer management, 722, Fig. 41A), the first field is arranged to indirectly indicate a buffer address (buffer stack index / top-of-stack pointer, 1058–1060, Fig. 60) of the network packet in the packet buffer (descriptor metadata associated with buffer identification rather than direct physical address storage, 722, Fig. 41A; buffer stack indexing, 1058–1060, Fig. 60), and the packet descriptor does not directly record the buffer address (buffer identification via stack/index abstraction rather than direct address pointer, 1058, Fig. 60); and a network processing unit (packet distribution engine and classifier processing packets based on descriptor information, 940, 950, Fig. 56), arranged to read the packet descriptor from the ring buffer (wait for descriptor from application and enqueue into hardware queue, 718–726, Fig. 41A), and perform predetermined packet processing of the network packet according to the packet descriptor (process packet header and distribute to worker, 1004, 1038–1046, Fig. 57; Fig. 59).
As to claim 2, Mattina discloses the network packet processing apparatus of claim 1, further comprising: a direct memory access (DMA) controller (iDMA engine / eDMA engine, 110, 112, Fig. 10; ingress DMA and egress DMA engines, 178, Fig. 14), comprising: a control circuit (DMA engine control logic, 178, Fig. 14), arranged to write the network packet into the packet buffer (write memory (PA), Fig. 11B; incoming buffers, 1050, Fig. 60), convert the buffer address of the network packet in the packet buffer into an address identification code (buffer stack index / top-of-stack identifier abstraction, 1058–1060, Fig. 60), and store the address identification code into the first field (descriptor metadata stored in command queue entry, 722, Fig. 41A).
As to claim 3, Mattina discloses the network packet processing apparatus of claim 2, wherein the packet buffer comprises a plurality of storage blocks used for storing a plurality of network packets, respectively (plural incoming buffers and backing store entries, 1050, Fig. 60), and the control circuit is arranged to map the plurality of storage blocks to a plurality of address identification codes, respectively (buffer stack indexing and push/pop mapping of buffer entries, 1058–1060, Fig. 60).
As to claim 4, Mattina discloses the network packet processing apparatus of claim 2, wherein the packet descriptor further comprises a second field (descriptor metadata field associated with status/control, 722, Fig. 41A); when the address identification code is stored into the first field, the DMA controller is further arranged to store a control code into the second field to indicate that processing of the packet descriptor is handed over to the NPU (put descriptor in hardware queue to signal processing by packet engine, 724–726, Fig. 41A).
As to claim 5, Mattina discloses the network packet processing apparatus of claim 2, wherein the packet descriptor further comprises a second field (descriptor metadata and result handling fields, 722, Fig. 41A); after reading the packet descriptor from the ring buffer (retrieve descriptor and process packet, 734–738, Fig. 41B), the NPU is further arranged to store a control code into the second field to indicate that processing of the packet descriptor is handed over to the DMA controller (add result to application queue and release buffer via push, 740, Fig. 41B; return buffer push, 1070, Fig. 61).
As to claim 6, Mattina discloses the network packet processing apparatus of claim 2, wherein the DMA controller further comprises: a buffer address pool (incoming buffers stack / backing store pool, 1050, 1058, Fig. 60), arranged to store a plurality of available buffer addresses in the packet buffer (buffer stack entries storing available buffer identifiers, 1058, Fig. 60); the control circuit is further arranged to read an available buffer address from the buffer address pool (pop operation retrieving available buffer, 1060, Fig. 60), and determine the buffer address of the network packet in the packet buffer according to the available buffer address (write memory (PA) using retrieved buffer identifier, Fig. 11B).
As to claim 7, Mattina discloses the network packet processing apparatus of claim 6, further comprising: a buffer management circuit (fill/spill control managing buffer stack usage, 1074–1076, Fig. 61), arranged to manage usage of the packet buffer (monitor TOS empty/full, 1072–1078, Fig. 61); wherein the DMA controller further comprises: a buffer address filling circuit (fill buffers control logic, 1074, Fig. 61), wherein the plurality of available buffer addresses are obtained through the buffer address filling circuit that requests the plurality of available buffer addresses from the buffer management circuit (fill buffers operation supplying stack entries, 1074, Fig. 61).
As to claim 8, Mattina discloses the network packet processing apparatus of claim 7, wherein a capacity of the buffer address pool is equal to M (buffer stack capacity parameter, Fig. 60), and when the buffer address pool is being initialized (initial fill condition when TOS empty, 1072–1074, Fig. 61), the buffer address filling circuit is arranged to request M available buffer addresses from the buffer management circuit, and store the M available buffer addresses into the buffer address pool (fill buffers populating stack, 1074, Fig. 61).
As to claim 9, Mattina discloses the network packet processing apparatus of claim 7, wherein a capacity of the buffer address pool is equal to M (buffer stack capacity, Fig. 60), and the buffer address filling circuit is arranged to monitor usage of the buffer address pool (TOS full/empty monitoring, 1072–1078, Fig. 61); when a number of available buffer addresses in the buffer address pool that are not used by the control circuit yet reaches A (threshold condition when TOS empty or below level, 1072, Fig. 61), the buffer address filling circuit is arranged to request (M-A) available buffer addresses from the buffer management circuit, and store the (M-A) available buffer addresses into the buffer address pool (fill buffers replenishment, 1074, Fig. 61).
As to claim 10, Mattina discloses a network packet processing apparatus comprising: a packet buffer (incoming buffers and backing store, 1050, Fig. 60), arranged to store a network packet; a ring buffer (software virtualized command queue and hardware command queue, 708–712, Fig. 40A), arranged to store a packet descriptor of the network packet (descriptor handling, 720–724, Fig. 41A), wherein the packet descriptor comprises a first field (descriptor metadata field, 722, Fig. 41A); and a direct memory access (DMA) controller (iDMA / eDMA engines, 110, 112, Fig. 10), comprising: a control circuit (DMA engine control logic, 178, Fig. 14), arranged to write the network packet into the packet buffer (write memory (PA), Fig. 11B), and store address-related information of a buffer address of the network packet in the packet buffer into the first field (buffer stack index stored in descriptor metadata, 722, Fig. 41A; 1058, Fig. 60).
As to claim 11, Mattina discloses the network packet processing apparatus of claim 10, further comprising: a network processing unit (packet distribution engine and classifier, 940, 950, Fig. 56), arranged to perform predetermined packet processing of the network packet according to the packet descriptor (process packet header and distribute to worker, 1004, Fig. 57); wherein the packet descriptor further comprises a second field (descriptor status/control metadata, 722, Fig. 41A); when the address-related information is stored into the first field, the DMA controller is further arranged to store a control code into the second field to indicate that processing of the packet descriptor is handed over to the NPU (put descriptor in hardware queue signaling processing, 724–726, Fig. 41A).
As to claim 12, Mattina discloses the network packet processing apparatus of claim 10, further comprising: a buffer address pool (incoming buffers stack, 1058, Fig. 60), arranged to store a plurality of available buffer addresses in the packet buffer; the control circuit is further arranged to read an available buffer address from the buffer address pool (pop operation, 1060, Fig. 60), and determine the buffer address of the network packet in the packet buffer according to the available buffer address (write memory using retrieved buffer identifier, Fig. 11B).
As to claim 13, Mattina discloses the network packet processing apparatus of claim 10, further comprising: a buffer management circuit (fill/spill control managing buffer usage, 1074–1076, Fig. 61), arranged to manage usage of the packet buffer; wherein the DMA controller further comprises: a buffer address filling circuit (fill buffers logic, 1074, Fig. 61), wherein the plurality of available buffer addresses are obtained through the buffer address filling circuit that requests the plurality of available buffer addresses from the buffer management circuit (fill buffers supplying stack entries, 1074, Fig. 61).
As to claim 14, Mattina discloses the network packet processing apparatus of claim 13, wherein a capacity of the buffer address pool is equal to M (buffer stack capacity, Fig. 60), and when the buffer address pool is being initialized (initial fill condition when empty, 1072–1074, Fig. 61), the buffer address filling circuit is arranged to request M available buffer addresses from the buffer management circuit, and store the M available buffer addresses into the buffer address pool (fill buffers populating stack, 1074, Fig. 61).
As to claim 15, Mattina discloses the network packet processing apparatus of claim 13, wherein a capacity of the buffer address pool is equal to M (buffer stack capacity, Fig. 60), and the buffer address filling circuit is arranged to monitor usage of the buffer address pool (TOS monitoring, 1072–1078, Fig. 61); when a number of available buffer addresses in the buffer address pool that are not used by the control circuit yet reaches A (threshold condition of reduced availability, 1072, Fig. 61), the buffer address filling circuit is further arranged to request (M-A) available buffer addresses from the buffer management circuit, and store the (M-A) available buffer addresses into the buffer address pool (fill buffers replenishment, 1074, Fig. 61).
Response to Arguments
Response to Arguments – Claim 1
Applicant argues that:
"Since the software-virtualized command queue 710 and the hardware command queue 712 taught by Mattina are used to store command descriptors sent from applications 708a, 708b, 708c, the software-virtualized command queue 710 and the hardware command queue 712 fail to read on the claim limitation 'a ring buffer, arranged to store a packet descriptor of the network packet, wherein the packet descriptor comprises a first field.'"
Applicant's argument is not persuasive.
Claim 1 merely recites "a ring buffer, arranged to store a packet descriptor of the network packet." The claim does not define the term "packet descriptor," nor does it distinguish a packet descriptor from a command descriptor. Likewise, the claim does not require that a packet descriptor be limited to any particular descriptor type or exclude a descriptor that contains information used to request, control, or facilitate processing of a network packet.
Mattina expressly teaches that accelerator circuitry performs network packet processing (Col. 11, ll. 35-40) and that acceleration engines use descriptor/result queues (also called rings) for communicating descriptors between software and accelerator hardware (Col. 80, ll. 42-47). Figures 40A and 41A further illustrate descriptors being stored in software-virtualized command queue 710 and hardware command queue 712 for subsequent processing by the accelerator. Because the disclosed descriptors are communicated through ring queues used in network packet processing, they reasonably correspond to the claimed packet descriptors under the broadest reasonable interpretation.
Applicant's argument assumes that a command descriptor cannot also constitute a packet descriptor. However, Applicant has not identified any language in claim 1 that distinguishes these descriptor types or excludes a command descriptor from also serving as the claimed packet descriptor. Such a limitation is not recited in the claim and therefore is not imported into the claim during examination.
Applicant further argues that:
"The buffer management taught by Mattina is based on buffer pointers. As known by those skilled in the pertinent art, a buffer pointer itself directly carries a buffer address. In other words, a buffer pointer is set by a buffer address. Therefore, buffer pointers taught by Mattina fail to anticipate the claim limitation 'the first field is arranged to indirectly indicate a buffer address of the network packet in the packet buffer, and the packet descriptor does not directly record the buffer address.'"
Applicant's argument is not persuasive.
Mattina expressly teaches storing and managing buffer pointers within a hardware-managed free buffer pool. Examiner acknowledges that Mattina describes the managed entries as buffer pointers. However, the rejection relies on the combination of Mattina's descriptor management and hardware-managed buffer allocation architecture. The claimed limitation merely requires that the first field indirectly indicate a buffer address and does not specify any particular encoding, identifier format, or translation mechanism by which the indirect indication is achieved. Under the broadest reasonable interpretation, a descriptor field identifying a packet buffer through a hardware-managed allocation mechanism reasonably satisfies this functional limitation.
Response to Arguments – Claim 10
Applicant argues that:
"Mattina does not teach or suggest that the iDMA engine is used to store the associated descriptor of the RX packet into the command descriptor sent from the application 708a/708b/708c. Therefore, Mattina fails to disclose 'a control circuit, arranged to write the network packet into the packet buffer, and store address-related information of a buffer address of the network packet in the packet buffer into the first field.'"
Applicant's argument is not persuasive.
Applicant's argument is premised on treating the application command descriptor of Figures 40A-41A and the packet-associated descriptor written by the iDMA engine of Figure 10 as mutually exclusive disclosures. The rejection, however, relies upon Mattina's disclosures as a whole. Mattina teaches that the iDMA engine writes both packet data and associated descriptors into memory for subsequent packet processing (Col. 33, ll. 22-30), while separately teaching descriptor rings used to communicate descriptors processed by accelerator hardware (Col. 80, ll. 42-47). One of ordinary skill in the art would have understood these disclosures together as describing DMA-assisted packet processing utilizing descriptors associated with network packets.
Furthermore, claim 10 does not require that the DMA controller store address-related information into an application-generated command descriptor. Rather, the claim broadly recites storing address-related information into the first field of a packet descriptor. Applicant's proposed interpretation improperly imports additional structural limitations concerning the origin and use of the descriptor that are not recited by the claim.
As such, examiner respectfully maintains the previous rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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