Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-21 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230134907 A1) in view of Song et al. (US 20210143180 A1).
Regarding claim 1: Lee discloses a nonvolatile memory device (100) comprising: cell strings (e.g., NS11 to NS33, FIG. 5) coupled between bit lines and source lines (between bit lines BL and common source line CSL, par. 82, FIG. 5), the cell strings including first select transistors (string selection transistor SST, par. 83, FIG. 5), memory cells (MC1-MC8, par. 83, FIG. 5), and second select transistors (ground selection transistor GST, par. 83, FIG. 5); first select lines (string selection lines SSL1-SSL3, par. 66, FIG. 5) coupled to the first select transistors (transistors SST coupled to lines SSL, FIG. 5) and spaced apart from each other in a direction in which the bit lines extend (lines SSL1-SSL3 spaced apart along bit line BL direction, FIG. 5); a voltage generator (500, FIG. 3) configured to, during an erase operation, apply a first turn-on voltage (turn on voltage VON1, FIG. 13) and apply a second turn-on voltage (turn on voltage VON2, FIG. 13); and a control circuit (450, FIG. 3) configured to control, after the first turn-on voltage reaches a target level (during erase operation, first high voltage ramping to a target level, par. 184) during the erase operation, the voltage generator so that the second turn-on voltage reaches the target level (after first voltage reaches target level, apply second high voltage ramping to the target level, par. 184).
Lee does not disclose a group of outer select lines among the first select lines, and inner select lines among the first select lines, the inner select lines being disposed between the outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E), inner select lines (second select gates of sub-blocks, can be inner blocks e.g., SUB-BLK1, par. 21, FIG. 1E), the inner select lines being disposed between the outer select lines (FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Regarding claim 2: Lee discloses a nonvolatile memory device (100) comprising: wherein the control circuit is configured to control the voltage generator so that the first turn-on voltage and the second turn-on voltage have a same target level (both first and second voltage ramping to the same target level, par. 184).
Regarding claim 3: Lee discloses a nonvolatile memory device (100) comprising: the control circuit is configured to control, when an erase voltage is applied to the bit lines and the source lines (erase voltage VERS applied to bit line and common source line, par. 129), the voltage generator (apply voltage to word lines, par. 129) to apply a first turn-on voltage (turn on voltage VON1, FIG. 13), and apply a second turn-on voltage (turn on voltage VON2, FIG. 13).
Lee does not disclose outer select lines and inner select lines.
Song does disclose a 3D NAND memory device (100) comprising: outer select lines (first select gates, can be outer blocks, par. 21, FIG. 1E) and inner select lines (second select gates, can be inner blocks, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Regarding claim 4: Lee discloses a nonvolatile memory device (100) comprising: wherein the control circuit is configured to control the voltage generator to apply a ground voltage to the outer select lines before the first turn-on voltage (ground voltage VSS before VON1, FIG. 13), and apply the ground voltage to the inner select lines before the second turn-on voltage (ground voltage VSS before VON2, FIG. 13).
Lee does not disclose applying the ground voltage to outer and inner select lines.
Song does disclose a 3D NAND memory device (100) comprising: outer select lines (first select gates, can be outer blocks, par. 21, FIG. 1E) and inner select lines (second select gates, can be inner blocks, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Regarding claim 5: Lee discloses a nonvolatile memory device (100), wherein the control circuit is configured to set a rising slope of the first turn-on voltage (turn on voltage VON1, FIG. 13) to have a first slope (rising slope of VON1, FIG. 13), and set a rising slope of the second turn-on voltage (turn on voltage VON2, FIG. 13) to have a second slope which is lower than the first slope (rising slope of VON2 is smaller than VON1, FIG. 13).
Regarding claim 7: Lee discloses a nonvolatile memory device (100), wherein the first select lines are drain select lines (string selection lines SSL, FIG. 3).
Regarding claim 12: Lee discloses a method for a nonvolatile memory device (100) comprising: applying an erase voltage to bit lines and a source line (erase voltage VERS applied to bit line and source line, par. 129); applying a first turn-on voltage (VON1) among first select lines among first select lines (string selection lines SSL, FIG. 3) adjacent to the bit lines (FIG. 3) and arranged in a different direction from a direction in which the bit lines are arranged (Lines SSL arranged along BL extension direction, different from the direction the BL1-BL3 are arranged, FIG. 3); applying a second turn-on voltage (VON2), wherein the second turn-on voltage has a rising slope lower than a rising slope of the first turn-on voltage (rising slope of VON2 is smaller than VON1, FIG. 13).
Lee does not disclose a group of outer select lines among the first select lines, and inner select lines among the first select lines, the inner select lines being disposed between the outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E), inner select lines (second select gates of sub-blocks, can be inner blocks e.g., SUB-BLK1, par. 21, FIG. 1E), the inner select lines being disposed between the outer select lines (FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Regarding claim 13: Lee discloses a method for a nonvolatile memory device (100), further comprising, before applying the first turn-on voltage, applying a ground voltage (ground voltage VSS before VON1, FIG. 13).
Lee does not disclose outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer select lines structure as the claimed invention.
Regarding claim 14: Lee discloses a method for a nonvolatile memory device (100), further comprising, before applying the second turn-on voltage, applying a ground voltage (ground voltage VSS before VON2, FIG. 13).
Lee does not disclose inner select lines.
Song does disclose a 3D NAND memory device (100) comprising: inner select lines (second select gates, can be inner blocks, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated inner select lines structure as the claimed invention.
Regarding claim 15: Lee discloses a method for a nonvolatile memory device (100), wherein the first and second turn-on voltages are set to have a same target level (both first and second voltage ramping to the same target level, par. 184).
Regarding claim 16: Lee discloses a method for a nonvolatile memory device (100), further comprising applying the first turn-on voltage (VON1) to second select lines (ground selection line GSL, FIG. 3) adjacent to the source line (common source line CSL, FIG. 3).
Lee does not disclose the first turn-on voltage applied to the outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer select lines structure as the claimed invention for the operation to apply the corresponding voltage to.
Regarding claim 17: Lee discloses a method for a nonvolatile memory device (100), wherein the first select lines are drain select lines (string selection lines SSL, FIG. 3) and the second select lines are source select lines (ground selection line GSL, FIG. 3).
Claim(s) 6, 8, 11, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230134907 A1) in view of Song et al. (US 20210143180 A1), in further view of Li et al. (US 20140226416 A1).
Regarding claim 6: Lee does not disclose inner select lines among the first select lines.
Song does disclose a 3D NAND memory device (100) comprising: inner select lines (second select gates, can be inner blocks, par. 21, FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated inner select lines structure as the claimed invention.
Lee and Song do not disclose the control circuit configured to control, before the second turn-on voltage is applied, the voltage generator to apply a negative voltage.
Li does disclose an erase operation with controlled select gate voltage bon-volatile memory, where before the second turn-on voltage (voltage VDD, par. 50) is applied, the voltage generator to apply a negative voltage (voltage Voff as a negative voltage applied prior to VDD, par. 50).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee and Song with the configuration of Li to allow the system to apply a negative voltage to the lines during the erase operation prior to the turn on voltage similar to the claimed invention.
Regarding claim 8: Lee discloses a method for a nonvolatile memory device (100), comprising: cell strings (e.g., NS11 to NS33, FIG. 5) coupled between bit lines and source lines (between bit lines BL and common source line CSL, par. 82, FIG. 5), the cell strings including first select transistors (between bit lines BL and common source line CSL, par. 82, FIG. 5), memory cells (MC1-MC8, par. 83, FIG. 5), and second select transistors (ground selection transistor GST, par. 83, FIG. 5); first select lines (string selection lines SSL1-SSL3, par. 66, FIG. 5) coupled to the first select transistors (transistors SST coupled to lines SSL, FIG. 5) and spaced apart from each other in a direction in which the bit lines extend (lines SSL1-SSL3 spaced apart along bit line BL direction, FIG. 5); a voltage generator (500, FIG. 3) configured to, during an erase operation, apply a first turn-on voltage (turn on voltage VON1, FIG. 13) and apply a second turn-on voltage (turn on voltage VON2, FIG. 13); and a control circuit (450, FIG. 3).
Lee does not disclose a group of outer select lines among the first select lines, and inner select lines among the first select lines, the inner select lines being disposed between the outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E), inner select lines (second select gates of sub-blocks, can be inner blocks e.g., SUB-BLK1, par. 21, FIG. 1E), the inner select lines being disposed between the outer select lines (FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Lee and Song do not disclose before the second turn-on is applied to the inner select lines during the erase operation, the voltage generator to apply a negative voltage to the inner select lines.
Li does disclose an erase operation with controlled select gate voltage bon-volatile memory, where before the second turn-on voltage (voltage VDD, par. 50) is applied to the inner select lines during the erase operation (erase operation, par. 48), the voltage generator to apply a negative voltage (voltage Voff as a negative voltage applied prior to VDD, par. 50) to the inner select lines.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Li to allow the system to apply a negative voltage to the lines during the erase operation prior to the turn on voltage similar to the claimed invention.
Regarding claim 11: Lee discloses a method for a nonvolatile memory device (100), wherein the first select lines are drain select lines (string selection lines SSL, FIG. 3).
Regarding claim 18: Lee discloses a method for a nonvolatile memory device (100), comprising: applying an erase voltage to bit lines and a source line (erase voltage VERS applied to bit line and common source line, par. 129); applying a ground voltage (VSS prior to turn on voltage VON, FIG. 13) among first select lines (string selection lines SSL1-SSL3, par. 66, FIG. 5) adjacent to the bit lines (FIG. 3) and arranged in a different direction from a direction in which the bit lines are arranged (Lines SSL arranged along BL extension direction, perpendicular to the direction the BL1-BL3 are arranged, FIG. 3); applying a first turn-on voltage to select lines to which the ground voltage is applied (turn on voltage VON1 after VSS, FIG. 13); applying a second turn-on voltage (turn on voltage VON2, FIG. 13) to the select lines.
Lee does not disclose a group of outer select lines among the first select lines, and inner select lines among the first select lines, the inner select lines being disposed between the outer select lines.
Song does disclose a 3D NAND memory device (100) comprising: select lines connected to sub blocks (FIG. 1E) with outer select lines (first select gates of sub-blocks, can be outer blocks e.g., SUB-BLK0, par. 21, FIG. 1E), inner select lines (second select gates of sub-blocks, can be inner blocks e.g., SUB-BLK1, par. 21, FIG. 1E), the inner select lines being disposed between the outer select lines (FIG. 1E).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Song to allow the system to have the designated outer and inner select lines structure as the claimed invention.
Lee and Song do not disclose applying a negative voltage to the inner select lines.
Li does disclose an erase operation with controlled select gate voltage bon-volatile memory, where before the second turn-on voltage (voltage VDD, par. 50) is applied to lines which a negative voltage is applied, the voltage generator to apply a negative voltage (voltage Voff as a negative voltage applied prior to VDD, par. 50).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Lee with the configuration of Li to allow the system to apply a negative voltage to the lines during the erase operation prior to the turn on voltage similar to the claimed invention.
Regarding claim 21: Lee discloses a method for a nonvolatile memory device (100), wherein the first select lines are drain select lines (string selection lines SSL, FIG. 3).
Allowable Subject Matter
Claims 9-10 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: following a negative voltage applied to a set of inner select lines, the control circuit is configured to control the voltage generator so that the first turn-on voltage and the second turn-on voltage reach a target level at a same time as in claim 9; following a negative voltage applied to a set of inner select lines, the control circuit is configured to set a rising slope of the second turn-on voltage to have a third slope which is steeper than the first slope as in claim 10; following a negative voltage applied to a set of inner select lines, the first and second turn-on voltages are set to have a same target level at a same time as in claim 19; and following a negative voltage applied to a set of inner select lines, wherein rising slope of the second turn-on voltage is steeper than a rising slope of the first turn-on voltage as in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights