Prosecution Insights
Last updated: July 17, 2026
Application No. 18/963,810

ORING FAULT DETECTION METHOD AND POWER SUPPLY SYSTEM

Non-Final OA §102
Filed
Nov 29, 2024
Priority
Dec 25, 2023 — CN 202311804202.7
Examiner
RHODES-VIVOUR, TEMILADE S
Art Unit
Tech Center
Assignee
Delta Electronics (Shanghai) Co., Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
722 granted / 814 resolved
+28.7% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
827
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
68.7%
+28.7% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Miller et al. (US PUB 2021/0152014), hereinafter Miller. (Figure 2 of Miller is provided below with annotation for the applicant’s convenience) PNG media_image1.png 440 610 media_image1.png Greyscale With respect to claim 1, Miller discloses an ORING fault detection method, which is applied to a power supply system (See figure 1 of Miller) comprising a plurality of power supply modules connected in parallel (See [102A]-[102N] in figure 1 of Miller), each power supply module comprising a primary unit (See [202] in figure 2 of Miller), a secondary unit (See [204] in figure 2 of Miller), an ORING unit (See [208] in figure 2 of Miller) and a control unit (See the annotated [A] in figure 2 of Miller), the primary unit (See [202] in figure 2 of Miller) and the secondary unit (See [204] in figure 2 of Miller) of each power supply module being connected (See the connection between [202] and [204] in figure 2 of Miller) and the ORING unit located at an output side of the secondary unit (See that [208] in figure 2 of Miller is connected to the output side of [204]), the control unit at least connected to the ORING unit (See that the annotated unit [A] is connected to the gate of [208] as shown in figure 2 of Miller above), the method comprising: starting the primary units of the plurality of power supply modules in a time-sharing manner (See paragraph [0015] in view of paragraph [0022] of Miller); starting the secondary units of the plurality of power supply modules within a first delay (See paragraph [0018] in view of paragraph [0022] of Miller); and as for each power supply module, if a bus voltage at an output end of the power supply module within the first delay is within a first threshold range (See paragraph [0013] in view of paragraph [0011] of Miller), initiating ORING detection of the power supply module (See paragraph [0011] in view of the abstract of Miller), comprising: determining whether the ORING unit is in a healthy state by judging whether an output current of the power supply module has a negative current, or whether a voltage difference before and after the ORING unit of the power supply module is less than a preset value (See paragraph [0011] of Miller which pertains to the first portion of the conditional OR statement). With respect to claim 11, Miller discloses the ORING fault detection method according to claim 1, wherein the bus voltage at the output end of the power supply module is a voltage at an output side of the ORING unit (See in figure 2 of Miller that the output of the ORING unit [208] is also the output of the power supply module [200]). With respect to claim 12, Miller discloses a power supply system, comprising: a plurality of power supply modules connected in parallel (See [102A]-[102N] in figure 1 of Miller), each power supply module comprising a primary unit (See [202] in figure 2 of Miller), a secondary unit (See [204] in figure 2 of Miller), an ORING unit (See [208] in figure 2 of Miller) and a control unit (See the annotated [A] in figure 2 of Miller), the primary unit and the secondary unit of each power supply module being connected (See the connection between [202] and [204] in figure 2 of Miller) and the ORING unit located at an output side of the secondary unit (See that [208] in figure 2 of Miller is connected to the output side of [204]), the control unit at least connected to the ORING unit (See that the annotated unit [A] is connected to the gate of [208] as shown in figure 2 of Miller above); wherein the control unit is configured to execute the ORING fault detection method according to claim 1 (See paragraph [0019] of Miller). Allowable Subject Matter Claims 2-10 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 2, the prior art of record neither shows nor suggests the combination of method steps further comprising: if the bus voltage at the output end of the power supply module is not within the first threshold range during the first delay, directly enabling the output of the secondary unit of the power supply module after the end of the first delay, and starting the secondary units of the plurality of power supply modules within a second delay. Claims 3-5, 9 and 10 depend from objected to claim 2 and are therefore also objected to. With respect to claim 6, the prior art of record neither shows nor suggests the combination of method steps wherein as for each power supply module, the ORING detection of the power supply module further comprises: if the output current of the power supply module has the negative current, or the voltage difference before and after the ORING unit is less than the preset value, determining that the ORING unit is in a faulty state; if the output current of the power supply module does not have the negative current, and the voltage difference before and after the ORING unit is not less than the preset value, determining that the ORING unit is in a normal state. Claim 7 depends from objected to claim 6 and is therefore also objected to. With respect to claim 8, the prior art of record neither shows nor suggests the combination of method steps further comprising: acquiring the output current of the power supply module through a current sampling unit connected to the output end of the secondary unit of the power supply module; acquiring a front-end voltage of the ORING unit of the power supply module through a first voltage sampling unit connected to a front end of the ORING unit of the power supply module; and acquiring a back-end voltage of the ORING unit of the power supply module through a second voltage sampling unit connected to a back end of the ORING unit of the power supply module; wherein the control units of the respective power supply modules acquire and perform ORING detection of the power supply module according to the corresponding output current of the respective power supply modules, or the front-end voltage and the back-end voltage of the corresponding ORING unit of the respective power supply modules. With respect to claim 13, the prior art of record neither shows nor suggests the combination of method steps wherein, each power supply module further comprises a plurality of input terminals and a plurality of output terminals; a first input terminal in the plurality of input terminals of each power supply module is connected to a live line of an AC power source, and a second input terminal in the plurality of input terminals of each power supply module is connected to a zero line of the AC power source; a first output terminal in the plurality of output terminals of each power supply module is connected to a positive end of the DC bus, and a second output terminal in the plurality of output terminals of each power supply module is connected to a negative end of the DC bus. Claims 14 and 15 depend from objected to claim 13 and are therefore also objected to. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PUB 2023/0221381 discloses fault detection methods and systems therefor. US PUB 2013/0181729 discloses a testing protection schemes of a power converter. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858 /HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Nov 29, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
96%
With Interview (+7.7%)
2y 6m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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