DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “ a size of the third transistor is smaller than a size of the fourth transistor” of claims 1 and 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (USP 6,919753).
Regarding claim 1, Wang et al.’s figure 3 shows A bandgap reference voltage generator, comprising: a first transistor (MN1), wherein a source electrode of the first transistor is coupled to a ground voltage via at least a first resistor (R1); a second transistor (MN2), wherein a source electrode of the second transistor is coupled to the ground voltage, and a gate electrode of the second transistor is coupled to a gate electrode of the first transistor; a third transistor (MP1), wherein a source electrode of the third transistor is coupled to a supply voltage (VDDA), and a drain electrode of the third transistor is coupled to a drain electrode of the first transistor; and a fourth transistor (MP2), wherein a source electrode of the fourth transistor is coupled to the supply voltage, and a drain electrode of the fourth transistor is coupled to a drain electrode of the second transistor via a second resistor (R2); wherein the bandgap reference voltage generator generates a reference voltage at the drain electrode of fourth transistor; and a size of the first transistor is greater than a size of the second transistor (MN1 is 8 times MN2; column 5, lines 25-30) as called for in claim 1.
Regarding claim 4, wherein the first transistor and the second transistor (MN1 and MN2) are N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and the third transistor and the fourth transistor (MP1 and MP2) are P-type MOSFET.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (USP 6,919753) in view of Hwang et al. (USP 8,405,376).
Regarding claim 2, Wang et al.’s figure 3 shows a bandgap reference voltage generator comprising all the aspects of the present invention as noted above except for third, fourth, fifth and sixth resistors as called for in claim 2.
Hwang et al.’s figure 4 shows teaches the use of resistors (R1, R2, R3) to reduce noises from the power supply (VDD) and the ground being introduced to the circuit, i.e., signal to noise ratio (column 4, lines 61-67; column 5, lines 57-67). Thus, it would have been obvious to persons skilled in the art before the effective filing date of the invention to include third, fourth, fifth and sixth resistors in Wang et al.’s circuit arrangement for the purpose of providing a reference voltage with a low noise as taught by Hwang et al. reference.
Regarding claim 3, the combination of Wang et al. and Hwang et al. reference does not teach wherein resistance of the first resistor combined with the third resistor is greater than resistance of the fourth resistor as called for in claim 3. However, it is noted that Wang et al.’s first resistor (R1) is a variable resistor which can be selected so that the generated reference voltage is least dependent on the temperature (see column 3, lines 10-67). The selection of the first resistor in combination of the third resistor resulted in a resistance that greater than the fourth resistor could have been a desired choice to obtain the reference voltage that is independent from the temperature. Therefore, outside of any non-obvious results, the obviousness of having resistance of the first resistor combined with the third resistor is greater than resistance of the fourth resistor for providing a reference voltage that is independent from temperature will not be patentable under 35USC 103.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (USP 6,919753) in view of Kong et al. (US 2023/0280774).
Regarding claim 5, Wang et al. shows a bandgap reference voltage generator comprising all the aspects of the present invention as note above except a buffer, configured to receive the reference voltage to generate an adjusted reference voltage, and the buffer comprises: an operational amplifier, wherein a first input terminal is used to receive the reference voltage; a trimming circuit, wherein an input terminal of the trimming circuit is connected to a second input terminal of the operational amplifier, and the trimming circuit is configured to generate adjusted reference voltage; and a transistor, controlled by a signal outputted by the operational amplifier, to selectively connecting the supply voltage to the trimming circuit as called for in claim 5.
Kong et al.’s figure 1 shows LDO regulator including a buffer comprising receive the reference voltage (Vreference) to generate an adjusted reference voltage (Vfeedback) , and the buffer comprises: an operational amplifier (102), wherein a first input terminal is used to receive the reference voltage; a trimming circuit (R1, R2), wherein an input terminal of the trimming circuit is connected to a second input terminal of the operational amplifier, and the trimming circuit is configured to generate adjusted reference voltage; and a transistor (103), controlled by a signal outputted by the operational amplifier, to selectively connecting the supply voltage to the trimming circuit. The buffer circuit is used to regulate and to provide a stable reference voltage via a feedback loop. Therefore, it would have been obvious to person skilled in the art before the effective filing of the invention to include Kong et al.’s buffer in Wang et al.’s circuit arrangement for providing a stable reference voltage as taught by Kong et al. reference.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (USP 6,919753) in view of Arnold et al. (US 2024/0143012) and Hwang et al. (USP 8,405,376).
Regarding claim 7, Wang et al.’s figure 3 shows A bandgap reference voltage generator, comprising: a first transistor (MN1), wherein a source electrode of the first transistor is coupled to a ground voltage via at least a first resistor (R1); a second transistor (MN2), wherein a source electrode of the second transistor is coupled to the ground voltage, and a gate electrode of the second transistor is coupled to a gate electrode of the first transistor; a third transistor (MP1), wherein a source electrode of the third transistor is coupled to a supply voltage (VDDA), and a drain electrode of the third transistor is coupled to a drain electrode of the first transistor; and a fourth transistor (MP2), wherein a source electrode of the fourth transistor is coupled to the supply voltage (VDDA), and a drain electrode of the fourth transistor is coupled to a drain electrode of the second transistor; wherein the bandgap reference voltage generator generates a reference voltage at the drain electrode of fourth transistor; and a size of the first transistor is greater than a size of the second transistor (MN1 is 8 times MN2; column 5, lines 25-30).
Wang et al. does not show: (1) a second resistor coupled between the first resistor and the ground voltage; (2) a third resistor, coupled between the source electrode of the second transistor and the ground voltage as called for in claim 7.
Regarding the difference noted in item (1), Wang et al.’s first resistor is a variable resistor which can be designed by a series of a two resistor (see Arnold et al.’s figure 3). Therefore, it would have been obvious to a person skilled in the art before the effective filing date of the invention to have Wang et al.’s variable resistor (R1) made with a series two resistors as taught by Arnold et al. reference.
Regarding the difference noted in item (2), Hwang et al.’s figure 4 shows teaches the use of resistors (R1, R2, R3) to reduce noises from the power supply (VDD) and the ground being introduced to the circuit, i.e., signal to noise ratio (column 4, lines 61-67; column 5, lines 57-67). Thus, it would have been obvious to persons skilled in the art before the effective filing date of the invention to include a third resistor in between the source electrode of the second transistor and ground for the purpose of minimizing the ground noise affecting the circuit as taught by Hwang et al. reference.
Regarding claim 8, Wang et al. reference does not show a fourth resistor, coupled between the source electrode of the third transistor and the supply voltage; and a fifth resistor, coupled between the source electrode of the fourth transistor and the supply voltage. Hwang et al.’s figure 4 shows teaches the use of resistors (R1, R2, R3) to reduce noises from the power supply (VDD) and the ground being introduced to the circuit, i.e., signal to noise ratio (column 4, lines 61-67; column 5, lines 57-67). Thus, it would have been obvious to persons skilled in the art before the effective filing date of the invention to include a fourth resistor and a fifth resistor in Wang et al.’s circuit arrangement for the purpose of minimizing the power supply noise affecting the circuit as taught by Hwang et al. reference.
Regarding claim 9, Wang et al. and Hwang et al. reference does not teach wherein resistance of the first resistor combined with the second resistor is greater than resistance of the third resistor as called for in claim 9. However, it is noted that Wang et al.’s first resistor (R1) is a variable resistor which can be selected so that the generated reference voltage is least dependent on the temperature (see column 3, lines 10-67). The selection of the first resistor in combination of the second resistor resulted in a resistance that greater than the fourth resistor could have been a desired choice to obtain the reference voltage that is independent from the temperature. Therefore, outside of any non-obvious results, the obviousness of having resistance of the first resistor combined with the second resistor is greater than resistance of the third resistor for providing a reference voltage that is independent from temperature will not be patentable under 35USC 103.
Regarding claim 10, wherein the first transistor and the second transistor (MN1 and MN2) are N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and the third transistor and the fourth transistor (MP1 and MP2) are P-type MOSFET.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (USP 6,919753) in view of Arnold et al. (US 2024/0143012) and Hwang et al. (USP 8,405,376) and further in view of Kong et al. (US 2023/0280774).
Regarding claim 11, the combination of Wang et al., Hwang et al. and Arnold et al. references shows a bandgap reference voltage generator comprising all the aspects of the present invention as note above except a buffer, configured to receive the reference voltage to generate an adjusted reference voltage, and the buffer comprises: an operational amplifier, wherein a first input terminal is used to receive the reference voltage; a trimming circuit, wherein an input terminal of the trimming circuit is connected to a second input terminal of the operational amplifier, and the trimming circuit is configured to generate adjusted reference voltage; and a transistor, controlled by a signal outputted by the operational amplifier, to selectively connecting the supply voltage to the trimming circuit as called for in claim 5.
Kong et al.’s figure 1 shows LDO regulator including a buffer comprising receive the reference voltage (Vreference) to generate an adjusted reference voltage (Vfeedback) , and the buffer comprises: an operational amplifier (102), wherein a first input terminal is used to receive the reference voltage; a trimming circuit (R1, R2), wherein an input terminal of the trimming circuit is connected to a second input terminal of the operational amplifier, and the trimming circuit is configured to generate adjusted reference voltage; and a transistor (103), controlled by a signal outputted by the operational amplifier, to selectively connecting the supply voltage to the trimming circuit. The buffer circuit is used to regulate and to provide a stable reference voltage via a feedback loop. Therefore, it would have been obvious to person skilled in the art before the effective filing of the invention to include Kong et al.’s buffer in Wang et al.’s circuit arrangement for providing a stable reference voltage as taught by Kong et al. reference.
Allowable Subject Matter
Claims 6 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 4/18/2026
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