DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11, 12-14, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 2021/0026763) and EP 4024219 (hereinafter EP219).
Regarding claim 1, KIM et al. discloses a storage device [FIG. 1: Storage Device] comprising: a non-volatile memory device comprising a user area including a plurality of first memory blocks [FIG. 14, ¶0007: NVM BLK, nonvolatile memory including a journal area], and a meta area comprising an address mapping table including address mapping information for the plurality of first memory blocks and a meta data mapping table including meta data for the address mapping table [¶0007, 0051, 0054, 0078: nonvolatile memory including a meta data area, update an address mapping table and store plurality of segments in the meta data area, a meta data kind may include the address mapping table AMT including information about page mapping between a logical address and a physical address], wherein the address mapping table includes a sub-address mapping table [¶0054: segments of the address mapping table AMT which are sub-address mapping table are stored in the meta data area], and the meta data mapping table includes meta data for the sub-address mapping table [¶0054: segments of the address mapping table AMT which are sub-address mapping table are stored in the meta data area]; and a storage controller configured to update at least one of the meta data to perform a first update operation and address mapping information of the sub-address mapping table to perform a second update operation [¶0071, 0082: controller writes or stores segment of the address mapping table in meta data area, the controller updates the address mapping table].
KIM et. Does not explicitly disclose flush the address mapping table into the meta area based on a result of the update.
EP219, however, discloses flush the address mapping table into the meta area based on a result of the update [¶0010: metadata region, map update operation and flushing write data stored in write buffer].
It would have been obvious to one of ordinary skill in the art to have flushed the address mapping table into the meta area based on a result of the update in order to ensure consistency between metadata and a log even when an unexpected event occurs (¶0004).
Regarding claims 11, 18, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 12, EP219 discloses the operation method of the storage device of claim 11, further comprising: loading the sub-address mapping table on which the second update operation was performed into the memory before the flushing [¶0010]; and aligning the sub-address mapping table loaded into the memory according to a predetermined program unit [¶0010].
Regarding claim 13, KIM et al. discloses the operation method of the storage device of claim 12, wherein: a size of the predetermined program unit is 16 Kilobytes (KB), and a size of the sub-address mapping table is 4 KB [¶0026, 0037].
Regarding claim 14, KIM et al. discloses the operation method of the storage device of claim 13, wherein: the aligning includes creating a dummy address mapping table of 4 KB size, and the flushing includes programing the dummy address mapping table to the non-volatile memory device [¶0026, 0031].
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 2021/0026763) and EP 4024219 (hereinafter EP219) and YANG (US 20210303476).
Regarding claim 2, KIM et al. discloses the storage device of claim 1, but does not explicitly disclose wherein: the meta area includes a plurality of second memory blocks that are different from the plurality of first memory blocks, and the plurality of second memory blocks are single level cell (SLC) blocks.
YANG, however, discloses the meta area includes a plurality of second memory blocks that are different from the plurality of first memory blocks, and the plurality of second memory blocks are single level cell (SLC) blocks [¶0030].
It would have been obvious to one of ordinary skill in the art to have the meta area including a plurality of second memory blocks that are different from the plurality of first memory blocks, and the plurality of second memory blocks are single level cell (SLC) blocks date in order to ensure the storing in the map buffer metadata including history information of a physical address mapped to a first logical address and updating the metadata stored in the map buffer based on mapping data for the first logical address depending on whether the mapping data for the first logical address has been updated (¶0007).
Claim(s) 3-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 2021/0026763) and EP 4024219 (hereinafter EP219) and KIM et al. (US 20210165604, hereinafter KIM II).
Regarding claim 3, KIM et al. discloses the storage device of claim 1, but does not explicitly disclose wherein the meta data includes a boost flag bit indicating consecutive placement of the address mapping information or an invalidity of the address mapping table, a starting page of a physical page number corresponding to a minimum logical page number of the address mapping table, and a table page of a physical address of the address mapping table.
KIM II, however, discloses the meta data includes a boost flag bit indicating consecutive placement of the address mapping information or an invalidity of the address mapping table, a starting page of a physical page number corresponding to a minimum logical page number of the address mapping table, and a table page of a physical address of the address mapping table [¶0143].
It would have been obvious to one of ordinary skill in the art to have the meta data includes a boost flag bit indicating consecutive placement of the address mapping information or an invalidity of the address mapping table, a starting page of a physical page number corresponding to a minimum logical page number of the address mapping table, and a table page of a physical address of the address mapping table in order to have nonvolatile memory devices fully realize the performance advantages offered by nonvolatile memory device (¶0005).
Regarding claim 4, KIM II discloses the storage device of claim 3, the boost flag bit is a logic high, and the starting page includes a valid physical address [¶0149].
Regarding claim 5, KIM II discloses the storage device of claim 3, the boost flag bit is a logic high, and the starting page includes vacant data [¶0149].
Regarding claim 6, KIM II discloses the storage device of claim 3, the boost flag bit is a logic low [¶0149].
Regarding claim 7, KIM et al. discloses the storage device of claim 1, wherein the storage controller includes a memory into which the sub-address mapping table is loaded [FIG. 3-8].
Regarding claim 8, KIM et al. discloses the storage device of claim 7, wherein the storage controller further includes a flash translation layer configured to perform the first and second update operations and load the sub-address mapping table into the memory [Abstract, ¶0005].
Regarding claim 9, KIM et al. discloses the storage device of claim 7, wherein the memory is a static random-access memory (SRAM) or a dynamic random-access memory (DRAM), and the first update operation is performed as an overwrite operation on the meta data mapping table [¶0027].
Regarding claim 10, KIM et al. discloses the storage device of claim 1, wherein the address mapping information includes a mapping between a logical page and a physical page in the user area [FIG. 3-8].
Claim(s) 15-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 2021/0026763) and EP 4024219 (hereinafter EP219) and Zeng et al. (US 2020/0272577).
Regarding claim 15, KIM et al. discloses the operation method of the storage device of claim 12, but does not explicitly disclose loading the sub-address mapping table on which the first update operation was performed into the memory before the flushing.
Zeng et al., however, discloses loading the sub-address mapping table on which the first update operation was performed into the memory before the flushing [¶0106, 0122].
It would have been obvious to one of ordinary skill in the art to have loaded the sub-address mapping table on which the first update operation was performed into the memory before the flushing in order to maintain associations between logical addresses and physical addresses of a storage drive (¶0003).
Regarding claim 16, Zeng et al. discloses the operation method of the storage device of claim 15, wherein: in the first update operation, an update for the address mapping information of the sub-address mapping table is not performed [¶0122].
Regarding claim 17, Zeng et al. discloses the operation method of the storage device of claim 16, wherein: in the flushing, the sub-address mapping table is program-skipped [¶0106].
Regarding claim 19, Zeng et al. discloses the storage system of claim 18, wherein: the host memory includes a host memory buffer allocated as a buffer of the storage device, the host memory buffer includes the address mapping table and the meta data mapping table, and the storage controller is configured to flush the address mapping table included in the host memory buffer into the meta area [¶0010, 0044, 0075].
Regarding claim 20, Zeng et al. discloses the storage system of claim 18, wherein: the first and second update operations are performed based on a write request for the data or a discard request for the data of the host [¶0122].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. YANG (US 20210303476) discloses memory controller wherein when mapping data for the logical address received from host is updated, the map update controller generates metadata based on the mapping data and stores generated metadata in the map buffer.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133