DETAILED ACTION
This office action is in response to the application filed on 11/29/2024. Claims 1-32 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawing
The drawing submitted on 11/29/2024 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/29/2024 and 05/01/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-15, 18-26, 29-32 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Saini (US Patent or PG Pub. No. 20220077776, hereinafter ‘776).
Claim 1, ‘776 teaches a floating ground generation circuit (e.g., 150, see fig. 2, 4, 5), comprising: a core biasing circuit (e.g., R1, R2, R4, M1, M2, M6, M14) configured to generate first and second reference voltages (e.g., Vth, Vdd-VRth at node connecting Rth and M6, see Fig. 4); a driver logic circuit (e.g., Mt1, Mt2, Mt3, M3, M7, D1, D2, Md) coupled to the core biasing circuit and configured to generate a floating ground voltage (e.g., Vfg in fig. 4) based on the first and second reference voltages (e.g., see Fig. 4); and a transient biasing circuit (e.g., M4, M5, M8-M13, R3, D1r, D2r) coupled to the driver logic circuit and configured to control transitions of the floating ground voltage between voltage levels (e.g., the voltage levels of p-PWM, see Fig. 2, 4),
wherein the driver logic circuit is configured to receive a floating supply reference signal (e.g., Gate signals of M3 and M7) and the transient biasing circuit is configured to generate a floating ground reference signal (e.g., Vfgrep, see [0020][0023]), the floating supply reference signal and floating ground reference signal being coordinated to control timing of the transitions between voltage levels (e.g., An n-channel MOSFET device M7 has a source and body connected to the drain of device M3 at floating ground output node 204 and a gate coupled to the gate of diode-connected device M6. An n-channel MOSFET device M8 has a source and body connected to the drain of device M4 at replica output node 206 and a gate coupled to the gate of diode-connected device M6, see [0020], Fig. 2, 4).
Claim 2, ‘776 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the core biasing circuit comprises: a voltage divider (e.g., R1, R2) coupled between a supply voltage and ground (e.g., Vdd and Gnd) to generate the first reference voltage; and a threshold voltage generator (e.g., Rth, R4, M2, M6, M14) the circuits comprising coupled to the supply voltage to generate the second reference voltage (e.g., the voltage at the drain gate of M6) that tracks process and temperature variations (e.g., both Fig. 4 of prior art and the Fig. 3 of Application disclose the exactly same voltage divider circuit and threshold voltage generator circuit, they are assumed producing the same tracking function as recited in the claim).
Claim 3, ‘776 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the voltage divider comprises: a first resistor (e.g., R1) connected between the supply voltage and a first node (e.g., the node connecting R1 and R2); and a second resistor (e.g., R2) connected between the first node and ground, wherein the first reference voltage is generated at the first node (e.g., see Fig. 4).
Claim 4, ‘776 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the threshold voltage generator comprises: a third resistor (e.g., Rth) connected between the supply voltage and a second node (e.g., the node connecting Rth and the drain gate of M6); and an n-channel transistor (e.g., M6) having its drain and gate connected to the second node, and its body connected to its source, wherein the second reference voltage is generated at the second node (e.g., see Fig. 4).
Claim 5, ‘776 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the driver logic circuit comprises: a level shifting circuit (e.g., the circuit comprising D1, D2, M7) configured to generate an intermediate voltage (e.g., the voltage at the node connection D1 and M7, see [0021], Fig. 4); a floating ground output circuit (e.g., M3, MT1) coupled to the level shifting circuit and configured to generate the floating ground voltage based on the intermediate voltage (e.g., Vfg being function of the voltage at the node connection D1 and M7, see [0021], Fig. 3); and a transient response circuit (e.g., the circuit comprising Mt2) configured to control discharge paths for the floating ground voltage (e.g., the path of Mt2 to Gnd, see Fig. 4).
Claim 8, ‘776 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the transient biasing circuit comprises: a diode-transistor cascade circuit (e.g., Dr1-Dr2, M8) configured to generate the floating ground reference signal that tracks supply voltage variations while maintaining voltage stress limits (e.g., see Fig. 4); a first control path (e.g., M5, M9, M10) configured to monitor operating state and adjust bias conditions (e.g., see Fig. 4); and a feedback loop (e.g., the loop circuit comprising M11, M12, M13, R3) configured to regulate current flow during transitions (e.g., see Fig. 4).
Claim 9, ‘776 teaches the limitations of claim 8 as discussed above. It further teaches that wherein the diode-transistor cascade circuit comprises: a first diode (e.g., D2) having an anode connected to the supply voltage (e.g., see Fig. 4); a second diode (e.g., Dr1) having an anode connected to a cathode of the first diode; and a transistor (e.g., M8) having its drain connected to a cathode of the second diode and its gate coupled to receive the second reference voltage (e.g., see Fig. 4).
Claim 10, ‘776 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the driver logic block includes compensation circuitry (e.g., the circuit comprising the capacitor-configured Md) configured to improve output impedance and settling time of the floating ground voltage (e.g., see [0020][0023], Fig. 4).
Claim 11, ‘776 teaches a floating supply voltage generation circuit (e.g., see Fig. 2, 4, 5), comprising: a core biasing block (e.g., R1’, R2’, R4’, M1’, M2’, M6’, M14) configured to generate first and second reference voltages (e.g., Vth’, VRth’, see Fig. 5); a driver logic block (e.g., Mt1’, Mt2’, Mt3’, M3’, M7’, D1’, D2’, Md’) coupled to the core biasing block and configured to generate a floating supply voltage (e.g., Vfs in fig. 4) based on the first and second reference voltages; and a transient biasing block (e.g., M4’, M5’, M8’-M13’, R3’, D1r’, D2r’) coupled to the driver logic block and configured to control transitions of the floating supply voltage between voltage levels (e.g., the voltage levels of n-PWM, see Fig. 2, 5), wherein the driver logic block is configured to receive a floating ground reference signal (Gate signals of M3’ and M7’) and the transient biasing block is configured to generate a floating supply reference signal (e.g., Vfsrep, see [0024][0027]), the floating ground reference signal and floating supply reference signal being coordinated to control timing of the transitions between voltage levels (e.g., A p-channel MOSFET device M4′ has a gate coupled to the gate of device M1′, a source connected to node 200 and a drain connected to replica output node 206′. A p-channel MOSFET device M8′ has a source and body connected to the drain of device M4′ at replica output node 206′ and a gate coupled to the gate of diode-connected device M6′, see [0024], Fig. 5).
Claim 12, ‘776 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the core biasing block comprises: a voltage divider (e.g., R1’, R2’) coupled between a supply voltage and ground (e.g., Vdd and Gnd) to generate the first reference voltage (e.g., see Fig. 5); and a threshold voltage generator (e.g., Rth’, R4’, M2’, M6’, M14’) coupled to the supply voltage to generate the second reference voltage (e.g., the voltage at the drain gate of M6) that tracks process and temperature variations (e.g., both Fig. 5 of prior art and the Fig. 4 of Application disclose the exactly same voltage divider circuit and threshold voltage generator circuit, they are assumed producing the same tracking function as recited in the claim).
Claim 13, ‘776 teaches the limitations of claim 12 as discussed above. It further teaches that wherein the voltage divider comprises: a first resistor (e.g., R1’) connected between the supply voltage and a first node (e.g., the node connecting R1’ and R2’); and a second resistor (e.g., R2’) connected between the first node and ground, wherein the first reference voltage is generated at the first node (e.g., see Fig. 5).
Claim 14, ‘776 teaches the limitations of claim 12 as discussed above. It further teaches that wherein the threshold voltage generator comprises: a resistor (e.g., Rth’) connected between a third node (e.g., the node connecting Rth’ and the drain gate of M6) and ground; a p-channel transistor (e.g., M6) having its source and body connected to a source of a transistor, its drain and gate connected to the third node, wherein the second reference voltage is generated at the third node (e.g., see Fig. 5).
Claim 15, ‘776 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the driver logic block comprises: a level shifting circuit (e.g., the circuit comprising D1’-D2’, M7’) configured to generate an intermediate voltage (e.g., the voltage at the node connection D2’ and M7’, see Fig. 5) ; a floating supply output circuit (e.g., the circuit comprising M3’, MT1’) coupled to the level shifting circuit and configured to generate the floating supply voltage based on the intermediate voltage (e.g., Vfs being function of the voltage at the node connection Dx and M7, see [0021], Fig. 5); and a transient response circuit (e.g., the circuit comprising Mt2’) configured to control charging paths for the floating supply voltage (e.g., the path of Mt2’ to Vdd, see Fig. 5).
Claim 18, ‘776 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the transient biasing block comprises: a diode-transistor cascade circuit (e.g., Dr1’-Dr2’, M8’) configured to generate the floating supply reference signal that tracks supply voltage variations while maintaining voltage stress limits (e.g., see Fig. 5); a first control path (e.g., M5’, M9’, M10’) configured to monitor operating state and adjust bias conditions; and a feedback loop (e.g., the loop circuit comprising M11’, M12’, M13’, R3’) configured to regulate current flow during transitions (e.g., see Fig. 5).
Claim 19, ‘776 teaches the limitations of claim 18 as discussed above. It further teaches that wherein the diode-transistor cascade circuit comprises: a first diode (e.g., Dr2’) having its anode connected to a drain of a transistor (e.g., M8’); a second diode (e.g., Dr1’) having its anode connected to a cathode of the first diode and its cathode connected to ground (e.g., see Fig. 5); and a p-channel transistor (e.g., M8’) having its source and body connected to a node (e.g., 206’) carrying the floating supply reference signal and its gate coupled to receive the second reference voltage (e.g., see Fig. 5).
Claim 20, ‘776 teaches the limitations of claim 11 as discussed above. It further teaches that wherein the driver logic block includes compensation circuitry (e.g., the circuit comprising the capacitor configured Md’) configured to improve output impedance and settling time of the floating supply voltage (e.g., see [0020][0023][0024][0027], Fig. 5).
Claim 21, ‘776 teaches a DC-DC converter system (e.g., see Fig. 2, 4, 5), comprising: a switching circuit (e.g., 100) configured to transfer power between an input and an output (e.g., Vdd and Vout); and a floating reference generation circuit (e.g., 150, 152. see Fig. 2, 4, 5) configured to provide a floating reference voltage (e.g., Vfg or Vfs) to the switching circuit, the floating reference generation circuit comprising: a core biasing block (e.g., R1, R2, R4, M1, M2, M6, M14, or R1’, R2’, R4’, M1’, M2’, M6’, M14’) configured to generate first and second reference voltages (e.g., Vth, Vdd-VRth of Fig. 4 or VRth of Fig. 5); a driver logic block (e.g., Mt1, Mt2, Mt3, M3, M7, D1, D2, Md and/or Mt1’, Mt2’, Mt3’, M3’, M7’, D1’, D2’, Md’) coupled to the core biasing block and configured to generate the floating reference voltage (e.g., Vfg in fig. 4 or Vfs in Fig. 5) based on the first and second reference voltages; and a transient biasing block (e.g., M4, M5, M8-M13, R3, D1r, D2r and/or M4’, M5’, M8’-M13’, R3’, D1r’, D2r’) coupled to the driver logic block and configured to control transitions of the floating reference voltage between voltage levels (e.g., the voltage levels of p-PWM and/or n-PWM, see Fig. 2), wherein the driver logic block is configured to receive a complementary reference signal (e.g., Vfg and/or Vfs) and the transient biasing block is configured to generate a local reference signal (e.g., Vfgrep and/or Vfsrep, see [0020][0023], Fig. 4, 5), the complementary reference signal and local reference signal being coordinated to control timing of the transitions between voltage levels (e.g., see Fig. 2, 4, 5).
Claim 22, ‘776 teaches the limitations of claim 21 as discussed above. It further teaches that wherein the floating reference voltage comprises one of: a floating ground voltage (e.g., Vfgrep of Fig. 4, see Fig. 2, 4) for referencing a low-side of the switching circuit; or a floating supply voltage (e.g., Vfsrep of Fig. 5, see Fig. 2, 5) for referencing a high-side of the switching circuit.
Claim 23, ‘776 teaches the limitations of claim 22 as discussed above. It further teaches that wherein the core biasing block comprises: a voltage divider (e.g., R1, R2) coupled between a supply voltage and ground (e.g., Vdd and Gnd) to generate the first reference voltage; and a threshold voltage generator (e.g., Rth, R4, M2, M6, M14) coupled to the supply voltage to generate the second reference voltage (e.g., the voltage at the drain gate of M6) that tracks process and temperature variations (e.g., both Fig. 4 of prior art and the Fig. 3 of Application disclose the exactly same voltage divider circuit and threshold voltage generator circuit, they are assumed producing the same tracking function as recited in the claim).
Claim 24, ‘776 teaches the limitations of claim 23 as discussed above. It further teaches that wherein the voltage divider comprises: a first resistor (e.g., R1) connected between the supply voltage and a first node (e.g., the node connecting R1 and R2); and a second resistor (e.g., R2) connected between the first node and ground, wherein the first reference voltage is generated at the first node. (e.g., see Fig. 4, 5)
Claim 25, ‘776 teaches the limitations of claim 23 as discussed above. It further teaches that wherein the threshold voltage generator comprises: a reference resistor (e.g., Rth) connected between one of: the supply voltage and a reference node (e.g., the node connecting M6 and Rth, see Fig. 4, or the node connecting M6’ and Rth’, see Fig. 5), or the reference node and ground (e.g., see Fig. 5); and a threshold transistor (e.g., M6 or M6’) having its control terminal and first current terminal connected to the reference node, wherein the second reference voltage is generated at the reference node (e.g., see Fig. 4, 5).
Claim 26, ‘776 teaches the limitations of claim 21 as discussed above. It further teaches that wherein the driver logic block comprises: a level shifting circuit (e.g., the circuit comprising D1-Dx, M7) configured to generate an intermediate voltage (e.g., the voltage at the node connection D1 and M7, see [0021], Fig. 4); an output circuit (e.g., M3, MT1) coupled to the level shifting circuit and configured to generate the floating reference voltage based on the intermediate voltage (e.g., Vfg being function of the voltage at the node connection D1 and M7, see [0021], Fig. 4); and a transient response circuit (e.g., the circuit comprising Mt2) configured to control current paths between the floating reference voltage and a fixed reference (e.g., the path of Mt2 to Gnd, see Fig. 4).
Claim 29, ‘776 teaches the limitations of claim 21 as discussed above. It further teaches that wherein the transient biasing block comprises: a diode-transistor cascade circuit (e.g., Dr1-Dr2, M8) configured to generate the local reference signal that tracks supply voltage variations while maintaining voltage stress limits (e.g., see Fig. 4); a first control path (e.g., M5, M9, M10 and/or M5’, M9’, M10’) configured to monitor operating state and adjust bias conditions (e.g., see Fig. 4, 5); and a feedback loop (e.g., the loop circuit comprising M11, M12, M13, R3 and/or M11’, M12’, M13’, R3’) configured to regulate current flow during transitions (e.g., see Fig. 4, 5).
Claim 30, ‘776 teaches the limitations of claim 29 as discussed above. It further teaches that wherein the diode-transistor cascade circuit comprises: a first diode (e.g., Dr2) coupled to the supply voltage; a second diode (e.g., Dr1) coupled to the first diode; and a cascade transistor (e.g., M8) coupled between the second diode and a node (e.g., 206) carrying the local reference signal, the cascade transistor having its control terminal coupled to receive the second reference voltage (e.g., see Fig. 4).
Claim 31, ‘776 teaches the limitations of claim 21 as discussed above. It further teaches that wherein the floating reference generation circuit is implemented as a floating ground generation circuit with the floating reference voltage comprising a floating ground voltage (e.g., Vfg), and wherein the complementary reference signal comprises a floating supply reference signal (e.g., Vfs, see Fig. 2, 4, 5).
Claim 32, ‘776 teaches the limitations of claim 21 as discussed above. It further teaches that wherein the floating reference generation circuit is implemented as a floating supply generation circuit (e.g., 152) with the floating reference voltage comprising a floating supply voltage (e.g., Vfs), and wherein the complementary reference signal comprises a floating ground reference signal (e.g., Vfgrep, see Fig. 2, 5).
Allowable Subject Matter
Claims 6-7, 16-17, 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 6, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a pull-down transistor having its gate coupled to receive the intermediate voltage and configured to control the floating ground voltage.
For claim 7, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the driver logic block further having: a first capacitor connected between a node carrying the intermediate voltage and ground to filter high-frequency noise.
For claim 16, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a pull-up transistor having its source connected to the supply voltage, its gate coupled to receive the intermediate voltage, and configured to control the floating supply voltage.
For claim 17, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the driver logic block further having: a first capacitor connected between a node carrying the intermediate voltage and ground to filter high-frequency noise.
For claim 27, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a pull-up transistor having its source connected to the supply voltage, its gate coupled to receive the intermediate voltage, and configured to control the floating supply voltage.
For claim 28, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the driver logic block further having: a first capacitor connected between a node carrying the intermediate voltage and ground to filter high-frequency noise.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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