DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, “…separating the sampling of a sampling object” in line 2 could be corrected to “…separating a sampling of a sampling object”. Appropriate correction is required.
In claim 1, “…odd-bit channel; and; an adder circuit…” in lines 4 – 5 should be corrected to “…odd-bit channel; and[[;]] an adder circuit…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the different even-bit data" in lines 3 – 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the different odd-bit data" in lines 6 – 7. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hollis (US 2009/0010320).
Re claim 1, Hollis teaches of a decision feedback equalizer for a double data rate memory (Abstract and Paragraph 0001), comprising: a sampling circuit (#136 and #130, Fig.4A), separating the sampling of a sampling object into even bits and odd bits (even data bits and odd data bits, Paragraphs 0031 and 0033), to output even-bit data on an even-bit channel (output of #110c-110d, Fig.4A), and to output odd-bit data on an odd-bit channel (output of #110a-110b, Fig.4A) (The input data signal is separated by the two paths 31a and 31b such that odd data bits of the incoming sequence are sampled at comparators 110a-110b on the rising edge of the clock, while even data bits in the sequence are sampled at comparators 110c-110d on the falling edge of the clock, Paragraph 0033); and; an adder circuit (Fig.4C) with parallel-to-serial conversion (multiplexers of #132, Fig.4A), coupled to the sampling circuit to receive the even-bit data and the odd-bit data (as shown in Fig.4A), and to combine (#112b of Fig.4C) the even-bit data with the odd-bit data (Dout(even) and Dout(odd) of Figures 4A and 4C) to generate full-rate data (Dout, Fig.4C and Paragraph 0046, Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hollis in view of Ko et al (US 2024/0429900).
Re claim 2, Hollis teaches of wherein: the sampling circuit uses a sampling clock to implement rising-edge and falling-edge sampling, and thereby the even-bit data and the odd-bit data are obtained (Paragraph 0033 and CLK, Fig.4A). Hollis does not specifically mention of the sampling clock being a first sampling clock and a second sampling clock.
Ko teaches of the sampling circuit uses a first sampling clock and a second sampling clock to implement rising-edge and falling-edge sampling, and thereby the even-bit data and the odd-bit data are obtained (complementary clock signals, Paragraph 0028).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the sampling clock be a first sampling clock and a second sampling clock so as to generate the even and odd data paths.
Re claim 3, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion organizes the even-bit data to generate even-bit half-rate data (from #114b, Fig.4A); and the adder circuit with parallel-to-serial conversion organizes the odd-bit data to generate odd-bit half-rate data (from #114a, Fig.4A) (half rate, Paragraph 0031).
Re claim 4, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion further modifies the first sampling clock as a third sampling clock that corresponds to the even-bit half-rate data; and the adder circuit with parallel-to-serial conversion further modifies the second sampling clock as a fourth sampling clock that corresponds to the odd-bit half-rate data (modified by delay, #116b) (the first and sampling clocks as taught by Ko, see claim 1).
Claims 5 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hollis and Ko in view of Huang et al (US 2025/0309920).
Re claim 5, Hollis teaches of wherein: multiple sampling objects (two data paths, #120a, #120b, Fig.4A) are received by the sampling circuit (#130, Fig.4A), which are contents that the memory (Paragraph 0001) receives and identifies based on different reference values (rising and falling edges, Paragraph 0033); and multiple even-bit data and multiple odd-bit data that correspond to the multiple sampling objects are obtained by the sampling circuit (even numbered data bits and odd numbered data bits, Paragraph 0031). Hollis does not specifically mention of the memory being a double data rate memory.
Huang teaches of synchronous Dynamic Random Access Memory (SDRAM), including Low-Power Double Data Rate (DDR) SDRAM, which may be referred to as DDR SDRAM, low-power DDR SDRAM, LPDDR SDRAM or, in some instances, LPDDRx where x describes the technology generation of the LPDDR SDRAM (Paragraph 0024).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the memory be a double data rate memory for improved power efficiency and higher memory capacities.
Re claim 6, Hollis teaches of further comprising: a selection circuit (#132, Fig.4A and Fig.4C), generating selection signals to control multiplexers in the adder circuit with parallel-to-serial conversion to organize the multiple even-bit data and the multiple odd-bit data to sort out the even-bit half-rate data and the odd-bit half-rate data, and form the full-rate data (selection signals to control multiplexers as shown in Fig.4A and 4C).
Re claim 7, Hollis teaches of: the selection circuit generates even-bit channel selection signals based on previous odd-bit data, to control the adder circuit with parallel-to-serial conversion; and the selection circuit generates odd-bit channel selection signals based on previous even-bit data, to control the adder circuit with parallel-to-serial conversion (previous odd and even bit data used to control the multiplexers as shown in Fig.4A).
Re claim 8, Hollis teaches of wherein: based on the even-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different even-bit data to generate an even-bit channel multiplexer output (#112b, see Fig.4A); based on the odd-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different odd-bit data to generate an odd-bit channel multiplexer output (#112a, see Fig.4A); and based on the even-bit channel multiplexer output and the odd-bit channel multiplexer output (Dout(odd) and Dou(even), Figures 4A and 4C), the adder circuit with parallel-to-serial conversion sorts out the even-bit half-rate data and the odd-bit half-rate data, and combines the even-bit half-rate data and the odd-bit half-rate data to form the full-rate data (output of multiplexer of Fig.4C).
Re claim 9, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion provides the odd-bit channel multiplexer output (from #112a, Fig.4A) to the selection circuit as the previous odd-bit data (as previous odd bit data for the incoming even bit data, Fig.4A); and the adder circuit with parallel-to-serial conversion provides the even-bit channel multiplexer output (from #112b, Fig.4A) to the selection circuit as the previous even-bit data (as previous even bit data for the incoming odd bit data, Fig.4A).
Allowable Subject Matter
Claims 10 – 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633
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