DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendment, filed June 19, 2026, with respect to the rejections of claims have been fully considered. Applicant's amendment necessitated the new grounds of rejection presented below by introducing the new reference of Chen et al (US 2015/0358005).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 7 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hollis (US 2009/0010320) in view of Chen et al (US 2015/0358005).
Re claim 1, Hollis teaches of a decision feedback equalizer for a double data rate memory (Abstract and Paragraph 0001), comprising: a sampling circuit (#136 and #130, Fig.4A), configured to receive multiple sampling objects identified based on different reference values (VREF+ΔV, VREF–ΔV, Fig.4A), separating the sampling of the multiple sampling objects into even bits and odd bits (even data bits and odd data bits, Paragraphs 0031 and 0033), to output multiple even-bit data on an even-bit channel (output of #110c-110d, Fig.4A), and to output multiple odd-bit data on an odd-bit channel (output of #110a-110b, Fig.4A) (The input data signal is separated by the two paths 31a and 31b such that odd data bits of the incoming sequence are sampled at comparators 110a-110b on the rising edge of the clock, while even data bits in the sequence are sampled at comparators 110c-110d on the falling edge of the clock, Paragraph 0033); and; an adder circuit (Fig.4C) with parallel-to-serial conversion (multiplexers of #132, Fig.4A), coupled to the sampling circuit to receive the multiple even-bit data and the multiple odd-bit data (as shown in Fig.4A), the adder circuit comprising multiplexers (multiplexers of #112a, #112b, Fig.4A) controlled by selection signals (each mux receives the output from the other mux as a control input, Paragraph 0035) to make a selection among the multiple even-bit data and make a selection among the multiple odd-bit data to sort out even-bit half-rate data and odd-bit half-rate data (Paragraph 0035, Fig.4A) and to combine (#112b of Fig.4C) the even-bit data with the odd-bit data (Dout(even) and Dout(odd) of Figures 4A and 4C) to generate full-rate data (Dout, Fig.4C and Paragraph 0046, Fig. 6). However, Hollis does not specifically teach of a selection circuit, generating the selection signals.
Chen teaches of a selection circuit, generating selection signals (#430, #432, Fig.4); and a circuit with parallel-to-serial conversion, coupled to the sampling circuit (sample latches, #330, #332, Fig.4) to receive the multiple even-bit data (from #330, Fig.4) and the multiple odd-bit data (from #332, Fig.4), the circuit comprising multiplexers (#420, #422, Fig.4) controlled by the selection signals (from the sample latches, #330, #332, Fig.4) to make a selection among the multiple even-bit data and make a selection among the multiple odd-bit data to sort out even-bit half-rate data and odd-bit half-rate data (Paragraphs 0048 – 0049).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a selection circuit for generating the selection signals to ensure that timing constraints for deciding the value of the preceding bit are met.
Re claim 7, Hollis teaches of: the selection circuit (as taught by Chen) generates even-bit channel selection signals based on previous odd-bit data, to control the adder circuit with parallel-to-serial conversion; and the selection circuit generates odd-bit channel selection signals based on previous even-bit data, to control the adder circuit with parallel-to-serial conversion (previous odd and even bit data used to control the multiplexers as shown in Fig.4A).
Re claim 8, Hollis teaches of wherein: based on the even-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different even-bit data to generate an even-bit channel multiplexer output (#112b, see Fig.4A); based on the odd-bit channel selection signals, the adder circuit with parallel-to-serial conversion makes a selection between the different odd-bit data to generate an odd-bit channel multiplexer output (#112a, see Fig.4A); and based on the even-bit channel multiplexer output and the odd-bit channel multiplexer output (Dout(odd) and Dou(even), Figures 4A and 4C), the adder circuit with parallel-to-serial conversion sorts out the even-bit half-rate data and the odd-bit half-rate data, and combines the even-bit half-rate data and the odd-bit half-rate data to form the full-rate data (output of multiplexer of Fig.4C).
Re claim 9, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion provides the odd-bit channel multiplexer output (from #112a, Fig.4A) to the selection circuit as the previous odd-bit data (as previous odd bit data for the incoming even bit data, Fig.4A); and the adder circuit with parallel-to-serial conversion provides the even-bit channel multiplexer output (from #112b, Fig.4A) to the selection circuit as the previous even-bit data (as previous even bit data for the incoming odd bit data, Fig.4A).
Claims 2 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hollis and Chen in view of Ko et al (US 2024/0429900).
Re claim 2, Hollis and Chen teach all the limitations of claim 1 as well as Hollis teaches of wherein: the sampling circuit uses a sampling clock to implement rising-edge and falling-edge sampling, and thereby the even-bit data and the odd-bit data are obtained (Paragraph 0033 and CLK, Fig.4A). Hollis and Chen do not specifically mention of the sampling clock being a first sampling clock and a second sampling clock.
Ko teaches of the sampling circuit uses a first sampling clock and a second sampling clock to implement rising-edge and falling-edge sampling, and thereby the even-bit data and the odd-bit data are obtained (complementary clock signals, Paragraph 0028).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the sampling clock be a first sampling clock and a second sampling clock so as to generate the even and odd data paths.
Re claim 3, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion organizes the even-bit data to generate even-bit half-rate data (from #114b, Fig.4A); and the adder circuit with parallel-to-serial conversion organizes the odd-bit data to generate odd-bit half-rate data (from #114a, Fig.4A) (half rate, Paragraph 0031).
Re claim 4, Hollis teaches of wherein: the adder circuit with parallel-to-serial conversion further modifies the first sampling clock as a third sampling clock that corresponds to the even-bit half-rate data; and the adder circuit with parallel-to-serial conversion further modifies the second sampling clock as a fourth sampling clock that corresponds to the odd-bit half-rate data (modified by delay, #116b) (the first and sampling clocks as taught by Ko, see claim 1).
Allowable Subject Matter
Claims 10 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARISTOCRATIS FOTAKIS/
Primary Examiner, Art Unit 2633
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