DETAILED ACTION
This office action is in response to the application filed on 11/29/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/29/2024 and 06/02/2025 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duong US 2017/0126118.
Regarding Claim 1, Duong teaches (Figures 1-6) a linear regulator (100) comprising: a compensation circuit (110) configured to generate a compensation voltage (from 110) based on a reference voltage (Vin) and a feedback voltage (Vfb), a voltage level of the compensation voltage (from 110) being changed based on a load current (output current) that is generated by an output voltage (Vout) and flows through an output terminal (at Vout); an adaptive gain control circuit (150-180) configured to track the load current (with 160 and 180) based on the compensation voltage (from 110), and to generate a first driving voltage (at V1) by adjusting a loop gain based on an amount of the load current; a buffer circuit (120) configured to generate a second driving voltage (at V2) by buffering the first driving voltage; a driver circuit (130) connected to the output terminal, and configured to generate the output voltage based on the second driving voltage; and a feedback circuit (140) connected to the output terminal, and configured to generate the feedback voltage based on the output voltage. (For Example: Par. 36-51)
Regarding Claim 2, Duong teaches (Figures 1-6) wherein, when the amount of the load current increases, the loop gain increases (see fig. 4), and wherein, when the amount of the load current decreases, the loop gain decreases (see fig. 4). (For Example: Par. 36-51)
Regarding Claim 16, Duong teaches (Figures 1-6) further comprising: a reference voltage generation circuit (producing VIN) configured to generate the reference voltage (VIN).
Regarding Claim 17, Duong teaches (Figures 1-6) wherein the linear regulator is connected to an output capacitor (CL) through the output terminal (with 190).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duong in view of KIM US 2013/0002216.
Regarding Claim 18, Duong teaches (Figures 1-6) the compensation circuit, the adaptive gain control circuit, the buffer circuit, the driver circuit and the feedback circuit are included in a semiconductor chip (the linear regulator 100 is on a chip, par. 136).
Duong does not teach wherein the output capacitor is located outside the semiconductor chip.
Kim teaches (Figures 1-2) wherein the output capacitor (CL at 300) is located outside the semiconductor chip (100). (For Example: Par. 44-48)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Duong to include wherein the output capacitor is located outside the semiconductor chip, as taught by Kim to improve output stability in the system.
Regarding Claim 19, Duong teaches (Figures 1-6 and 20) an electronic device (300) comprising: a first semiconductor chip (320), par. 136) including a linear regulator configured to provide an output voltage through an output terminal (par. 133); an output capacitor (Cl) connected between the output terminal and a ground voltage (Fig. 1); a linear regulator (100) comprising: a compensation circuit (110) configured to generate a compensation voltage (from 110) based on a reference voltage (Vin) and a feedback voltage (Vfb), a voltage level of the compensation voltage (from 110) being changed based on a load current (output current) that is generated by an output voltage (Vout) and flows through an output terminal (at Vout); an adaptive gain control circuit (150-180) configured to track the load current (with 160 and 180) based on the compensation voltage (from 110), and to generate a first driving voltage (at V1) by adjusting a loop gain based on an amount of the load current; a buffer circuit (120) configured to generate a second driving voltage (at V2) by buffering the first driving voltage; a driver circuit (130) connected to the output terminal, and configured to generate the output voltage based on the second driving voltage; and a feedback circuit (140) connected to the output terminal, and configured to generate the feedback voltage based on the output voltage. (For Example: Par. 36-51)
Duong does not teach a second semiconductor chip configured to receive the output voltage as a power supply voltage.
Kim teaches (Figures 1-2) a second semiconductor chip (300) configured to receive the output voltage as a power supply voltage (load). (For Example: Par. 44-48)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Duong to include a second semiconductor chip configured to receive the output voltage as a power supply voltage, as taught by Kim to improve output stability in the system.
Allowable Subject Matter
Claim 3-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 13; prior art of record fails to disclose either by itself or in combination: “…wherein the adaptive gain control circuit includes: a current source connected between an input voltage and a first node; a first transistor connected between the first node and a ground voltage, and having a gate electrode connected to the first node; a second transistor connected to a second node configured to receive the compensation voltage, and having a gate electrode connected to the first node; a third transistor connected between the second transistor and the ground voltage, and having a gate electrode connected to the second node; a fourth transistor connected between the second node and the ground voltage, and having a gate electrode connected to the second node; and a fifth transistor connected between the ground voltage and a third node configured to provide the first driving voltage, and having a gate electrode connected to the second node”.
Claim 20; prior art of record fails to disclose either by itself or in combination: “…wherein the adaptive gain control circuit includes: a current source connected between an input voltage and a first node; a first transistor connected between the first node and a ground voltage, and having a gate electrode connected to the first node; a second transistor connected to a second node configured to receive the compensation voltage, and having a gate electrode connected to the first node; a third transistor connected between the second transistor and the ground voltage, and having a gate electrode connected to the second node; a fourth transistor connected between the second node and the ground voltage, and having a gate electrode connected to the second node; and a fifth transistor connected between the ground voltage and a third node configured to provide the first driving voltage, and having a gate electrode connected to the second node, wherein, when the amount of the load current increases, the loop gain increases and the loop gain is determined based on a gain of the fourth transistor, and wherein, when the amount of the load current decreases, the loop gain decreases and the loop gain is determined based on a gain of the second transistor and a gain of the third transistor”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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