Prosecution Insights
Last updated: April 19, 2026
Application No. 18/964,422

DATA RECEIVING CIRCUIT AND MEMORY

Non-Final OA §112
Filed
Nov 30, 2024
Examiner
ALI, SHAWKAT M
Art Unit
2633
Tech Center
2600 — Communications
Assignee
Cxmt Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
569 granted / 640 resolved
+26.9% vs TC avg
Strong +20% interview lift
Without
With
+20.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
14 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
3.7%
-36.3% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
7.7%
-32.3% vs TC avg
§112
36.6%
-3.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims 2. This communication is responsive to Application No. 18/964,422 filed on November 30, 2024. Claims 1-15 are subject to examination. Specification/Drawings 3. Specification/drawings are objected because paragraph 75 of the specification recites “a first NMOS transistor N01, where the control terminal is used to receive the first adjustment sub-signal SS1” and “a second NMOS transistor N02, where the control terminal is used to receive the second adjustment sub-signal SS2”. In figure 7, however, it appears that the “N01” is receiving “SS3” and the “N02” is receiving “SS4”. Appropriate correction is required. Also note that the lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification. Claim Objections 4. Following claims are objected to because of the following informalities: in claim 1, “each of the plurality of data paths receiving the double-ended signals, wherein the i-th” (line 8) should be replaced with “wherein each of the plurality of data paths receives the double-ended signals, the i-th”; in claim 4, “NMOS transistor” (line 3) should be replaced with “n-channel metal-oxide semiconductor (NMOS) transistor”; and in claim 5, “PMOS transistor” (line 2) should be replaced with “p-channel metal-oxide semiconductor (PMOS) transistor”. Appropriate correction is required. Claim Interpretations 5. The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. –An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 6. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the “i-th data path is configured to sample” in claim 1. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If Applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, Applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 7. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 8. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention. Claim 1 recites the limitation "the input data" in line 3. There is insufficient antecedent basis for this limitation in the claim. Hence, renders claim 1 and its dependent claims indefinite. Since in claim 3 between lines 1 and 2 (the limitations: “the doubled ended adjustment signals comprise…” [and/or?] “the sampling circuit comprises…”) a coordinator (e.g., and, or) is missing, it is not clear whether the limitations in claim 3 is referring to all the limitations or just one of them. Reason for Allowance 9. Tajalli (US 11,632,114 B2) teaches in Figure 2 a comparator (220 “MIC0”), a plurality of paths (230 (x4)) and a sampling circuit (“Sampler”). Bhagavathula (US 2014/0092951 A1) teaches in Figure 3 a comparator (310), an adjustment circuit (315) and a sampling circuit (320). Gu (US 11,777,484 B2) teaches in Figure 9 a comparator (901). However, with regard to claim 1, the prior art of record fails to disclose said i-th data path (Figure 1: 20, Figures 2-3, 6: 102, Figure 5: 201 & Figure 7: 202) as claimed in “combination” with “the corresponding structure, material or act : described in the Applicant’s Specification as performing the entire claimed function and [or] equivalents thereof” where applicable under 35 U.S.C 112(f). Conclusion 10. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to SHAWKAT M. ALI whose telephone number is (571) 270-1639. The Examiner can normally be reached on Monday-Thursday 8:30AM-3:30PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO AIR at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, SAM K. AHN can be reached on (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAWKAT M ALI/ Primary Examiner, Art Unit 2633
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Prosecution Timeline

Nov 30, 2024
Application Filed
Jan 24, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+20.3%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allow rate.

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