Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-7, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2016/0372518 A1, hereinafter referred to as Li).
Regarding Claims 1, Li discloses: A semiconductor integrated-circuit (IC) chip (100, Figs. 1, 2) comprising:
a first magnetoresistive-random-access-memory (MRAM) cell ("A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor", Abstract, para 0005, and FIG. l);
a second magnetoresistive-random-access-memory (MRAM) cell having a first terminal coupling to a first terminal of the first magnetoresistive-random-access-memory (MRAM) cell ("a pinned layer of a first MTJ device may be coupled to the bit line and a free layer of a second MTJ device may be coupled to the bit line" (first terminals of both MRAM cells coupled at shared BL), para 0004, FIG. 1);
a first transistor having a channel coupling to a second terminal of the first magnetoresistive-random-access-memory (MRAM) cell ("a second terminal (e.g., a drain) of the first access transistor 102 may be coupled to the free layer of the first MTJ device 104" (channel of first transistor to second terminal of first cell), para 0024, FIG. l); and
a second transistor having a channel coupling to a second terminal of the second magnetoresistive-random-access-memory (MRAM) cell ("a second terminal (e.g., a drain) of the second access transistor 106 may be coupled to the pinned layer of the second MTJ device 108" (channel of second transistor to second terminal of second cell), para 0026, FIG. 1).
Regarding Claims 2, Li discloses: wherein the first transistor has a gate terminal coupling to a gate terminal of the second transistor ("A gate terminal of the first access transistor 102 may be coupled to a word line (WL)", para 0024, Fig. 1; and "A gate terminal of the second access transistor 106 may be coupled to the word line (WL)" (shared WL/gate), para 0026, FIG. 1).
Regarding Claims 5-7, Li discloses the additional third and fourth transistors (mapped to the dual access transistors used for programming paths), wherein the third transistor is turned on for coupling the first magnetoresistive-random-access-memory (MRAM) cell to a programming voltage through the channel of the third transistor for programming the first magnetoresistive-random-access-memory (MRAM) cell, and wherein the fourth transistor is turned on for coupling the second magnetoresistive-random-access-memory (MRAM) cell to a voltage of ground reference through the channel of the fourth transistor for programming the second magnetoresistive-random-accessmemory (MRAM) cell ("To program the first MTJ device 104 to the parallel state, the first source line (SL1) is biased to a logical high voltage level (Vhigh) ... and the bit line (BL) is biased to ... ground" (third transistor channel turned on to Vprog); and equivalent differential biasing for the second cell to ground reference path (para 0035, FIG. 3).
Regarding Claims 18, Li discloses: wherein the first magnetoresistive-random-access-memory (MRAM) cell is programmed at a first resistance and the second magnetoresistive-random-access-memory (MRAM) cell is programmed at a second resistance lower than the first resistance ("Because the MTJ devices 104, 108 are included in a complementary bit cell ... the state of the first MTJ device 104 is opposite of the state of the second MTJ device 108. For example, if the first MTJ device 104 is programmed to the parallel state, then the second MTJ device 108 is programmed to the anti-parallel state" (one low resistance, one high resistance), para 0022, FIGS. 1, 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, 8-14, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kardasz et al. (US9728712B2, hereinafter referred to as Kardasz).
Regarding Claims 3, 4, 8, and 9, Li discloses all the features and limitations as discussed above and further disclose: the first transistor and second transistor (and the third/fourth programming transistors mapped to the same access transistors used for write) are N-type metal-oxide-semiconductor (MOS) transistors ("In a particular aspect, the first access transistor 102 is an n-type metal oxide semiconductor (NMOS) transistor", para 0024, Fig. 1; and "the second access transistor 106 is an NMOS transistor", para 0026, FIG. 1).
Li does not disclose a P-type first/third transistor. Kardasz does not disclose transistor conductivity types.
It would have been obvious to a person of ordinary skill in the art to substitute a P-type MOS transistor for the first (and third) transistor while keeping the second (and fourth) as N-type because complementary CMOS (PMOS pull-up to Vprog + NMOS pull-down to ground) is a standard, well-known technique in MRAM write-assist circuits (explicitly motivated by Li's differential SLI /SL2 biasing to Vhigh/ground), yielding predictable performance improvements when combined with the shared-BL cell of Li and the MTJ stack of Kardasz.
Regarding Claims 10-14, Li discloses the base structure of claim 1 (as mapped above).
Li does not disclose the specific MTJ layer materials.
Kardasz discloses each of the limitations of claims 10-14 (MgO oxide, Co/Fe/B first magnetic layer) ("Tunneling barrier layer 216 is disposed over reference layer 215, and can comprise a layer of MgO having a thickness of 0.5 nm to 2.0 nm" (oxide layer = magnesium oxide), col. 7, ll. 33+, FIG. 2; "Reference layer 215 ... can comprise a CoFeB layer" and "Free layer 218 ... can comprise a layer of CoFeB" (first magnetic layer comprises cobalt (Co), iron (Fe), boron (B)), col. 7, ll. 32+, FIG. 2).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the exact MTJ stack of Kardasz into the bit cell of Li because Kardasz teaches that MgO provides a high tunnel magnetoresistance (TMR) ratio, CoFeB enables low switching current and stable anisotropy, thereby improving data retention and power efficiency in the 2T-2MTJ structure of Li with no more than predictable results.
Regarding Claims 19-20, Li discloses all the features and limitations as discussed above and further disclose: The semiconductor integrated-circuit (IC) chip of claim 1 is a logic chip / is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip ("The STT-MRAM device may be integrated in a mobile phone, a communications device, a personal digital assistant (PDA), a tablet ... or an entertainment unit" (logic chip), para 0019); and "the array ... may be integrated into a wireless device", para 0047 (obvious extension to nonvolatile logic/FPGA configuration memory).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kardasz and further in view of Pietambaram et al. (US8497538B2, hereinafter referred to as Pietambaram).
Regarding Claim 16, the modified Li discloses all the features and limitations as discussed above.
Li and Kardasz do not disclose wherein the antiferromagnetic layer comprises chromium (Cr).
Pietambaram discloses: wherein the antiferromagnetic layer comprises chromium (Cr) ("anti-ferromagnetic coupling spacer layers 65 and 66 include at least one of the elements Ruthenium, Rhodium, Chromium, Vanadium, Molybdenum, for example, or combinations thereof and alloys of these such as Ruthenium-Tantalum" (and this applies to the synthetic antiferromagnet structure used for pinning/fixed layers in the MRAM bit) (col. 4, ll. 42+, FIGS. 1-3 and claim 3).
Therefore, it would have been obvious to a person of ordinary skill in the art to substitute chromium (Cr) as taught in Pietambaram for the antiferromagnetic pinning/coupling material in the combined Li and Kardasz structure because Pietambaram explicitly enumerates Cr as a conventional material for achieving anti-ferromagnetic coupling in MRAM synthetic antiferromagnet structures, providing strong exchange bias for pinning the magnetization direction of the fixed/reference layer, thereby enhancing thermal stability and operational reliability with no more than predictable results.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kardasz and further in view of Deak (US20060192304Al, hereinafter referred to as Deak).
Regarding Claim 17, the modified Li discloses all the features and limitations as discussed above.
Li and Kardasz do not disclose wherein the antiferromagnetic layer comprises iron (Fe).
Deak discloses: wherein the antiferromagnetic layer comprises iron (Fe) ("Other exemplary materials for the pinning layer 22 include, but are not limited to, FeMn, PtMn, and NiMn" (antiferromagnetic pinning layer comprises iron (Fe) via FeMn) (para 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art to substitute the FeMn anti ferromagnetic pinning layer taught in Deak for the generic AFM layer of the combined Li and Kardasz structure because Deak explicitly lists FeMn as a conventional pinning material that provides strong exchange coupling and stable magnetization pinning in MRAM devices, yielding predictable improvements in thermal stability with no more than predictable results.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Andre (US 9,472,256 B1) discloses magnetic memory having two transistors and two magnetic tunnel junctions per memory cell.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844