Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0105556 (Joung) in view of US 2014/0298303 (Kanada).
With regard to claim 1, Joung discloses a network packet processing apparatus comprising:
a direct memory access (DMA) controller, arranged to write a network packet into the first memory (Joung: Paragraph [0018]);
a network processing unit (NPU), arranged to read the partial packet content, and perform packet pre-processing of the network packet according to the partial packet content (Joung: Abstract and Paragraph [0048]. Joung provides for the processing of a packet header for pre-processing the packets.).
Joung fails to disclose, but Kanada teaches:
a first memory; a second memory, wherein an access latency of the second memory is lower than an access latency of the first memory (Kanada: Paragraph [0006]. Kanada provides two memory locations, a SRAM storage (faster but more expensive) for storing the header and DRAM that can store the entire packet.);
that the DMA controller is arranged to write a partial packet content of the network packet into the second memory (Kanada: Paragraph [0006] and Joung: Paragraph [0017]. When presented with the use of DMA to reduce processor load and increase I/O speed, such would be used for both packet transfers when Joung is modified with Kanada.); and
a network processing unit (NPU), arranged to read the partial packet content from the second memory (Kanada: Paragraph [0006]. The packet portions are stored to be read by the system, which when applied to Joung, would have the portions stored in the corresponding memories and read to perform the pre-processing.).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing to store the packet header in SRAM and the packet in DRAM to balance storage capacity with cost while allowing the system to process the packets according to a queue (Kanada: Paragraphs [0006] to [0007]).
With regard to claim 2, Joung in view of Kanada teaches that the partial packet content comprises a header of the network packet (Joung: Abstract and Kanada: Paragraph [0006]).
With regard to claim 3, Joung in view of Kanada teaches wherein the first memory is a dynamic random access memory, and the second memory is a static random access memory (Kanada: Paragraphs [0006] and [0003]).
With regard to claim 4, Joung in view of Kanada fails to teach, but knowledge possessed by oen of ordinary skill in the art at the time of filing teaches that the DMA controller comprises: a memory synchronization circuit; and an address sniffing circuit, arranged to allocate an address memory to be monitored, monitor at least one write address at which the DMA controller performs writing upon the first memory, and trigger the memory synchronization circuit to write the partial packet content into the second memory when the address memory to be monitored hits the at least one write address (More specifically, Official Notice is taken that the linking of memory locations, such that when data is written to one location, the data is partially mirrored to the other location, was well-known to one of ordinary skill in the art.). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing to provide a memory synchronization unit that monitors/checks a memory location for written data (e.g. a packet) and makes a partial mirror of that data (e.g. a header of the packet) to enable the system to present one memory for writing the data (thus presenting a single queue for the packets), while benefiting from the increased speed of the SRAM by positioning the packet header in SRAM closer to when it is to be utilized, thus decreasing the amount of SRAM required by the system, thus providing further cost savings versus storing every packet header (Kanada: Paragraph [0006]).
With regard to claim 7, Joung fails to disclose, but Joung does teaches, wherein the NPU is further arranged to create and maintain a sniffer list; the sniffer list comprises a plurality of entries for recording a plurality of memory addresses of the first memory that are available for a plurality of network packets, respectively; and the address sniffing circuit is further arranged to obtain the address memory to be monitored from the sniffer list (Joung: Paragraph [0064]. Joung utilizes pointers to identify the location of data items, where when applied to the tracking of the packet storage locations, a listing of pointers identifying the storage locations of the packets would be able to be used.). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing to use pointers to store the location of the packets to allow for the efficient queuing and tracking of stored packets regardless of the specific organization of the DRAM.
With regard to claim 6, the instant claim is within the scope of claim 7, and is rejected for similar reasons.
With regard to claim 8, Joung in view of Kanada, fails to teach, but knowledge possessed by one of ordinary skill in the art at the time of filing teaches teaches wherein the NPU writes memory addresses into the sniffer list through a data structure of a ring buffer, and the address sniffing circuit reads memory addresses from the sniffer list through the data structure of the ring buffer (More specifically, Official Notice is taken that the use of a ring buffer for writing and reading data was known to one of ordinary skill in the art.). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing to utilize a ring buffer for writing memory addresses to the pointer list (sniffer list) to provide an efficient and known technique for the reading and writing of data, where a ring buffer provides a structured and predictable set of data within memory that would prevent fragmentation, as a ring buffer would provide a specific number of spaces for storing the data, with the data always being accessed in a FIFO manner. Further, the use of buffers in general would prevent possible overflows in cases where data is to be read or written faster than the system could handle, specifically during a spike, allowing the accesses to be spread over a longer period of time rather than simply being dropped.
With regard to claim 9, Joung in view of Kanada teaches that the data structure of the ring buffer is arranged to record a plurality of packet descriptors that correspond to the plurality of network packets, respectively; and the sniffer list is maintained through the plurality of packet descriptors (Joung: Paragraph [0064]. The pointers would at least describe the location of the packets.).
With regard to claim 10, Joung in view of Kanada teaches, wherein the second memory comprises a storage space; the storage space is divided into a plurality of storage blocks used for storing a plurality of partial packet contents that correspond to the plurality of network packets, respectively; and a number of the plurality of entries included in the sniffer list is equal to a number of the plurality of storage blocks included in the storage space (Kanada: Paragraph [0006] and Joung: Paragraph [0064]. When providing a pointer list, such as in Joung, the pointer list would serve to divide the memory into a number of spaces to store the data.).
With regard to claims 11-14 and 16-20, the instant claims are similar to claims 1-4 and 6-10, and are rejected for similar reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT B CHRISTENSEN whose telephone number is (571)270-1144. The examiner can normally be reached Monday through Friday, 6AM to 2PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Follansbee can be reached at (571) 272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SCOTT B. CHRISTENSEN
Examiner
Art Unit 2444
/SCOTT B CHRISTENSEN/Primary Examiner, Art Unit 2444
Prosecution Insights