Prosecution Insights
Last updated: July 17, 2026
Application No. 18/964,727

Codec system and its encoding circuit and decoding circuit

Non-Final OA §102
Filed
Dec 02, 2024
Priority
Dec 06, 2023 — TW 112147534
Examiner
JEAN PIERRE, PEGUY
Art Unit
Tech Center
Assignee
Realtek Semiconductor Corporation
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
984 granted / 1044 resolved
+34.3% vs TC avg
Minimal -1% lift
Without
With
+-0.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
9 currently pending
Career history
1051
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1044 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/2/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Basappa et al. (US 2010/0134332). With regard to claim 1, Basappa diswcloses: A codec system, comprising: a minimum change code generation circuit (Gray code 500 Fig. 5; 204 Fig. 2) configured to generate a digital code; a flag generation circuit coupled to the minimum change code generation circuit (206 Fig. 2; 204 Fig. 3) and configured to generate a flag based on the digital code; and a decoding circuit (502 fig 5) configured to decode the digital code according to a preset value (the output of adder is input into 2:1 multiplexer 510, and the remaining bits of the intermediate value (e.g., all bits but the most significant bit) are input into the 2:1 multiplexer 510) and the flag to generate an output value.. Allowable Subject Matter Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 12-20 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Williams (US 6,345,008); Martekk (US 4,785,282) discloses minimum code change device.. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105. /PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Dec 02, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683624
DUAL ARBITRATION AND INTERLEAVED SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC)
2y 3m to grant Granted Jul 14, 2026
Patent 12683618
CURRENT-OUTPUT DIGITAL-TO-ANALOG CONVERTER
1y 9m to grant Granted Jul 14, 2026
Patent 12676627
ANALOG-TO-DIGITAL CONVERTER AND SEMICONDUCTOR DEVICE HAVING THE SAME
2y 6m to grant Granted Jul 07, 2026
Patent 12676626
ANALOG-TO-DIGITAL CONVERTER
2y 3m to grant Granted Jul 07, 2026
Patent 12676630
DIGITAL-TO-ANALOG CONVERTER AND APPARATUS INCLUDING THE SAME
1y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
94%
With Interview (-0.7%)
1y 8m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1044 resolved cases by this examiner. Grant probability derived from career allowance rate.

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