Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the amendment filed 3/31/2026 in which Claims 1-10 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 4, 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2024/0223412 to Peng et al (“Peng”) in view of U.S. Patent 7,535,396 to Melanson in further view of U.S. Patent Publication 2022/0038205 to Mukherjee et al (“Mukherjee”).
As to Claim 1, Peng teaches a control circuit for a feed-forward equalizer (FFE), the FFE having a plurality of tap drivers commonly coupled to an output terminal (The FFE includes an output [output terminal], a plurality of tap drivers, and a control circuit, see Abstract; The FFE 107 mainly includes output stage circuits 110-1 to 110-3, an output, and a control circuit 150, see ¶ 0025; conversion of a single-ended input into a differential output is taken as an example for the output stage circuits 110-1 to 110-3. As a result, this embodiment includes two outputs Dout and DoutB. The two outputs Dout and DoutB are configured to output differential signals, see ¶ 0026; Outputs of the tap drivers 140-1 to 140-5 are coupled to the outputs Dout and DoutB, see ¶ 0029),
an impedance control loop, coupled to the FFE controller, to generate a second reference voltage according to the at least one first reference voltage, and output the second reference voltage to at least one second tap driver among the plurality of tap drivers (The FFE control loop 151 includes a first replica circuit corresponding to the cell driver included in a part of the tap drivers (e.g., the pre-tap driver 140-1 and the post-tap driver 140-5). The FFE control loop 151 generates one or more first reference voltages according to the first replica circuit. A part of the tap drivers (the pre-tap driver 140-1 and the post-tap driver 140-5) is controlled by the one or more first reference voltages to adjust respective output impedance thereof. The impedance control loop 152 includes a second replica circuit corresponding to the cell drivers 145-1 to 145-5 in the tap drivers 140-1 to 140-5. The impedance control loop 152 generates one or more second reference voltages based on the one or more first reference voltages and the second replica circuit, see ¶ 0031);
Peng does not expressly disclose an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage.
Melanson teaches an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage (a digital-to-analog converter (DAC) in accordance with an embodiment of the present invention is shown. A digital input is supplied to a delta-sigma modulator 10 [DAC] operated by a sampling clock 13 that provides an input to a finite impulse response (FIR) filter 12. FIR filter 12 may be one of multiple parallel filters used to implement a DAC for improved matching, or may implement a single filter. The output of FIR filter 12 is provided to an output stage 16 that converts the differential current provided by a set of tap current sources 17 [FFE controller to receive a basic current from a current generator] into a voltage output, see Col. 3, lines 24-31; The current sources are summed to provide an analog output, which is typically converted either internally or externally to a voltage representing the digital value…the DACs output may be a current output that mirrors the current outputs generated by the DAC elements [current mirror coupled to the current DAC to mirror the reference current to generate a reference voltage], see Col. 1, lines 17-20, 32-35).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Peng with Melanson to teach an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage.
The suggestion/motivation would have been in order for each pair of current sources must be well-matched, as well as the matching typically required among the individual taps (see Col. 1, lines 45-47).
Peng and Melanson do not expressly disclose the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers.
Mukherjee teaches the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers (a current mirror circuit coupled between a tap of the loop filter and a current mirror output node; a low pass filter coupled between the current mirror output node and the reference voltage; a voltage buffer selectively coupled between the current mirror output node and a tap of the low pass filter by a first switch [first tap driver], see ¶ 0009; The current mirror 16 generates its output as the mirrored voltage Vmirr at node N3 [current mirror output at least one first reference voltage to a first tap driver]. A low-pass filter is formed by a resistor Rf coupled between node N3 and N4 and a capacitor Cf coupled between node N4 and the reference voltage, see ¶ 0022).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Peng and Melanson with Mukherjee to teach the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers. The suggestion/motivation would have been in order for a constant current to operate together with a current controlled by a control voltage (see ¶ 0006).
As to Claim 3, Peng, Melanson and Mukherjee depending on Claim 1, Peng teaches wherein the current mirror comprises: a replica channel; an input channel coupled to the replica channel through a first node having one of the at least one first reference voltage; and a mirror channel, coupled to the replica channel through a second node having another one of the at least one first reference voltage (The FFE control loop 151 includes a first replica circuit corresponding to the cell driver included in a part of the tap drivers (e.g., the pre-tap driver 140-1 and the post-tap driver 140-5). The FFE control loop 151 generates one or more first reference voltages according to the first replica circuit. A part of the tap drivers (the pre-tap driver 140-1 and the post-tap driver 140-5) is controlled by the one or more first reference voltages to adjust respective output impedance thereof. The impedance control loop 152 includes a second replica circuit corresponding to the cell drivers 145-1 to 145-5 in the tap drivers 140-1 to 140-5. The impedance control loop 152 generates one or more second reference voltages based on the one or more first reference voltages and the second replica circuit, see ¶ 0031).
As to Claim 4, Peng, Melanson and Mukherjee depending on Claim 3, Peng teaches wherein the replica channel is a replica of one of the at least one first tap driver (The FFE control loop 151 includes a first replica circuit corresponding to the cell driver included in a part of the tap drivers (e.g., the pre-tap driver 140-1 and the post-tap driver 140-5). The FFE control loop 151 generates one or more first reference voltages according to the first replica circuit. A part of the tap drivers (the pre-tap driver 140-1 and the post-tap driver 140-5) is controlled by the one or more first reference voltages to adjust respective output impedance thereof, see ¶ 0031; all the tap drivers (including the main-tap driver, the pre-tap controller, and the post-tap controller) are copied together with a reference voltage, see ¶ 0020).
As to Claim 6, Peng, Melanson and Mukherjee depending on Claim 1, Peng teaches wherein the plurality of tap drivers comprise a pre-tap driver, a post-tap driver and a main-tap driver (The tap driver 140-1 is driven by pre-tap data, and is thus also referred to as a pre-tap driver. The tap drivers 140-2 to 140-4 are driven by main tap data, and are thus also referred to as main-tap drivers. The tap driver 140-5 is driven by post-tap data, and is thus also referred to as a post-tap driver, see ¶ 0029).
As to Claim 7, Peng, Melanson and Mukherjee depending on Claim 6, Peng teaches wherein the at least one first tap driver comprises the pre-tap driver and the post-tap driver, and the at least one second tap driver comprises the main-tap driver (The tap driver 140-1 is driven by pre-tap data, and is thus also referred to as a pre-tap driver. The tap drivers 140-2 to 140-4 are driven by main tap data, and are thus also referred to as main-tap drivers. The tap driver 140-5 is driven by post-tap data, and is thus also referred to as a post-tap driver, see ¶ 0029).
As to Claim 8, Peng, Melanson and Mukherjee depending on Claim 1, Peng teaches wherein the FFE controller determines the at least one first reference voltage for pre-emphasis or de-emphasis of the FFE (Since output impedance of the pre-tap driver 140-1 and the post-tap driver 140-5 in FIG. 1 has been fixed by the first reference voltages Vrefn.pre and Vrefn.post generated based on the first loop circuits 310 and 320, see ¶ 0048).
As to Claim 9, Peng, Melanson and Mukherjee depending on Claim 1, Peng teaches wherein the impedance control loop determines the at least one second reference voltage according to the at least one first reference voltage, to control the plurality of tap drivers to generate a current corresponding to a characteristic impedance (The FFE control loop 151 includes a first replica circuit corresponding to the cell driver included in a part of the tap drivers (e.g., the pre-tap driver 140-1 and the post-tap driver 140-5). The FFE control loop 151 generates one or more first reference voltages according to the first replica circuit. A part of the tap drivers (the pre-tap driver 140-1 and the post-tap driver 140-5) is controlled by the one or more first reference voltages to adjust respective output impedance thereof. The impedance control loop 152 includes a second replica circuit corresponding to the cell drivers 145-1 to 145-5 in the tap drivers 140-1 to 140-5. The impedance control loop 152 generates one or more second reference voltages based on the one or more first reference voltages and the second replica circuit, see ¶ 0031).
As to Claim 10, Peng teaches a feed-forward equalizer (FFE), comprising: an output circuit, comprising a plurality of tap drivers commonly coupled to an output terminal; and a control circuit, coupled to the output circuit (The FFE includes an output [output terminal], a plurality of tap drivers, and a control circuit, see Abstract; The FFE 107 mainly includes output stage circuits 110-1 to 110-3, an output, and a control circuit 150, see ¶ 0025; conversion of a single-ended input into a differential output is taken as an example for the output stage circuits 110-1 to 110-3. As a result, this embodiment includes two outputs Dout and DoutB. The two outputs Dout and DoutB are configured to output differential signals, see ¶ 0026; Outputs of the tap drivers 140-1 to 140-5 are coupled to the outputs Dout and DoutB, see ¶ 0029),
an impedance control loop, coupled to the FFE controller, to generate a second reference voltage according to the at least one first reference voltage, and output the second reference voltage to at least one second tap driver among the plurality of tap drivers (The FFE control loop 151 includes a first replica circuit corresponding to the cell driver included in a part of the tap drivers (e.g., the pre-tap driver 140-1 and the post-tap driver 140-5). The FFE control loop 151 generates one or more first reference voltages according to the first replica circuit. A part of the tap drivers (the pre-tap driver 140-1 and the post-tap driver 140-5) is controlled by the one or more first reference voltages to adjust respective output impedance thereof. The impedance control loop 152 includes a second replica circuit corresponding to the cell drivers 145-1 to 145-5 in the tap drivers 140-1 to 140-5. The impedance control loop 152 generates one or more second reference voltages based on the one or more first reference voltages and the second replica circuit, see ¶ 0031).
Peng does not expressly disclose an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage.
Melanson teaches an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage (a digital-to-analog converter (DAC) in accordance with an embodiment of the present invention is shown. A digital input is supplied to a delta-sigma modulator 10 [DAC] operated by a sampling clock 13 that provides an input to a finite impulse response (FIR) filter 12. FIR filter 12 may be one of multiple parallel filters used to implement a DAC for improved matching, or may implement a single filter. The output of FIR filter 12 is provided to an output stage 16 that converts the differential current provided by a set of tap current sources 17 [FFE controller to receive a basic current from a current generator] into a voltage output, see Col. 3, lines 24-31; The current sources are summed to provide an analog output, which is typically converted either internally or externally to a voltage representing the digital value…the DACs output may be a current output that mirrors the current outputs generated by the DAC elements [current mirror coupled to the current DAC to mirror the reference current to generate a reference voltage], see Col. 1, lines 17-20, 32-35).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Peng with Melanson to teach an FFE controller to receive a basic current from a current generator, comprising: a current digital-to-analog converter (DAC) to generate a reference current according to the basic current; and a current mirror, coupled to the current DAC, to mirror the reference current to generate at least one first reference voltage.
The suggestion/motivation would have been in order for each pair of current sources must be well-matched, as well as the matching typically required among the individual taps (see Col. 1, lines 45-47).
Peng and Melanson do not expressly disclose the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers.
Mukherjee teaches the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers (a current mirror circuit coupled between a tap of the loop filter and a current mirror output node; a low pass filter coupled between the current mirror output node and the reference voltage; a voltage buffer selectively coupled between the current mirror output node and a tap of the low pass filter by a first switch [first tap driver], see ¶ 0009; The current mirror 16 generates its output as the mirrored voltage Vmirr at node N3 [current mirror output at least one first reference voltage to a first tap driver]. A low-pass filter is formed by a resistor Rf coupled between node N3 and N4 and a capacitor Cf coupled between node N4 and the reference voltage, see ¶ 0022).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Peng and Melanson with Mukherjee to teach the control circuit comprising: a current mirror to output the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers. The suggestion/motivation would have been in order for a constant current to operate together with a current controlled by a control voltage (see ¶ 0006).
Claim(s) 2, 5 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2024/0223412 to Peng et al (“Peng”) in view of U.S. Patent 7,535,396 to Melanson in further view of U.S. Patent Publication 2022/0038205 to Mukherjee et al (“Mukherjee”) and in further view of U.S. Patent Publication 2017/0019275 to Norimatsu.
As to Claim 2, Peng, Melanson and Mukherjee depending on Claim 1, Peng, Melanson and Mukherjee do not expressly disclose wherein the current generator generates the basic current by using a bandgap voltage, or using a power voltage with a voltage divider resistor. Norimatsu teaches wherein the current generator generates the basic current by using a bandgap voltage, or using a power voltage with a voltage divider resistor (the reference current source 1001 is composed of a band gap circuit, see ¶ 0091).
Before the effective filing date of the claimed invention, it would have been
obvious to one of ordinary skill in the art to modify Peng, Melanson and Mukherjee with Norimatsu to teach wherein the current generator generates the basic current by using a bandgap voltage, or using a power voltage with a voltage divider resistor. The suggestion/motivation would have been in order to receive a reference value 712 of a reference current or a reference voltage from the reference value generation circuit 711 and convert input data into an analog voltage or current with resolutions proportional to the reference value (see ¶ 0074).
As to Claim 5, Peng, Melanson and Mukherjee depending on Claim 1, Peng, Melanson and Mukherjee do not expressly disclose wherein the current DAC receives a control data, which determines a value of the reference current. Norimatsu teaches wherein the current DAC receives a control data, which determines a value of the reference current (a control signal (DAC_SW<2:0>) of each of the switches 1006 to 1008 is the DAC resolution switch signal 802 and a least significant bit <0> is connected to the switch 1006, a second bit <1> is connected to the switch 1007, and a third bit <2> is connected to the switch 1008…the current flowing to the current source circuit 1009 is changed by a value of the DAC resolution switch signal 802 [current DAC], the reference value 712 (voltage: TAP BIAS) distributed to the individual DACs 706 to 710 is changed, and the resolution of each DAC is switched, see ¶ 0092).
Before the effective filing date of the claimed invention, it would have been
obvious to one of ordinary skill in the art to modify Peng, Melanson and Mukherjee with Norimatsu to teach wherein the current DAC receives a control data, which determines a value of the reference current. The suggestion/motivation would have been in order for the reference value distributed to the individual DACs is changed (see ¶ 0092).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EBONI N GILES whose telephone number is (571)270-7453. The examiner can normally be reached Monday - Friday 9 am - 6 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached at (571)272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
Prosecution Insights