DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054.
Regarding claim 1, Singh discloses an artificial intelligent processing unit (APU) (paragraph [0002]: Learning machines discussed in this disclosure may fall under the technological titles of machine learning, artificial intelligence, neural networks, probabilistic inference engines, accelerators, and the like), comprising:
a plurality of hosts (external device, image sensor, image signal processor (ISP));
a plurality of external data processing accelerator (EDPA) interfaces, respectively coupled to the plurality of hosts (paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; see fig. 3 and fig. 4 configurable accelerator framework (CAF) 400); and
at least one EDPA, optionally coupled to the plurality of EDPA interfaces (paragraph [0120]: Multiple accelerators, grouped or chained together, handle varying sizes for feature maps data and multiple kernels in parallel. Grouping the convolutional accelerators (CA's) 600 to achieve larger computational entities enables choosing an acceptably optimal balancing of the available data bandwidth, budget power, and available processing resources; see fig. 4 configurable accelerator framework (CAF) 400),
wherein the plurality of EDPA interfaces are configured as interfaces between the plurality of hosts and the at least one EDPA (paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a (interfaces between external hosts and accelerators 600), a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c (interfaces between ISP hosts and accelerators 600). Other interfaces are also contemplated; see fig. 3 and fig. 4 configurable accelerator framework (CAF) 400).
Singh discloses all the features with respect to claim 1 as outlined above. However, Singh fails to disclose the number of the plurality of EDPA interfaces is more than the number of the at least one EDPA explicitly.
Venkatesan discloses the number of the plurality of EDPA interfaces is more than the number of the at least one EDPA (col. 5 line 24-29: the AI accelerator 110 may include more than one interface controller 150. Further, functionality attributed to a component of the AI accelerator 110 may be accomplished by a different component included in the AI accelerator 110, by the cache allocation module 120, or by a different system; col. 8 line 61-64: the interface controller 150 may be a network interface controller that can allow communication among the cores on the same network using cables or wirelessly; each AI accelerator has plurality of interfaces both internal and external).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh’s to use multiple interfaces as taught by Venkatesan, to dynamic cache allocation in AI accelerators.
Regarding claim 2, Singh as modified by Venkatesan discloses the APU of claim 1, wherein the plurality of hosts comprise at least one of an image signal processor (ISP), a display, a deep learning accelerator (DLA), a vision processing unit (VPU), and a virtual machine (VM) (Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh’s to use multiple interfaces as taught by Venkatesan, to dynamic cache allocation in AI accelerators.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, and further in view of Zhao U.S. Patent Application 20240354367.
Regarding claim 3, Singh as modified by Venkatesan discloses plurality of EDPA interfaces (Singh's paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated). However, Singh as modified by Venkatesan fails to disclose upon determining that the plurality of hosts comprise at least one VPU, at least one of the interfaces is configured as a register used to store instructions accessible by the at least one VPU for controlling at least one of the at least one EDPA.
Zhao discloses upon determining that the plurality of hosts comprise at least one VPU, at least one of the interfaces is configured as a register used to store instructions accessible by the at least one VPU for controlling at least one of the at least one EDPA (paragraph [0041]: The data is then transferred from the “global memory” to a shared memory and/or register(s) of the graphics processor 132, VPU 138 and/or AI accelerator 148).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to use register as taught by Zhao, to load data based on an order of operations associated with the data.
Claim 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, and further in view of Sin U.S. Patent Application 20210225320.
Regarding claim 4, Singh as modified by Venkatesan discloses upon determining that the plurality of hosts comprise an ISP and a display, two EDPA interfaces of the plurality of EDPA interfaces are configured respectively coupled to the ISP and the display (Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources). However, Singh as modified by Venkatesan fails to disclose two interfaces of the plurality of interfaces are configured as hardware sync engines (HSEs) explicitly.
Sin discloses two interfaces of the plurality of interfaces are configured as hardware sync engines (HSEs) (paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Regarding claim 5, Singh as modified by Venkatesan and Sin discloses the APU of claim 4, wherein one of the two EDPA interfaces coupled to the ISP is configured to sync operations order between the ISP and at least one of the at least one EDPA,
wherein while the ISP sending raw image data to a DRAM buffer, the one EDPA interface coupled to the ISP informs the at least one of the at least one EDPA, and then the at least one of the at least one EDPA is enabled to read the raw image data from the DRAM buffer (Sin’s paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260; paragraph [0100]: a display driver integrated circuit (e.g., the display driver integrated circuit 261 of FIG. 2) included in the display may read the first frame 33a stored in the buffer memory at a time point obtained by adding an offset 337 to a first time point 335a of the second synchronization period and at a time point obtained by adding the offset 337 to a second time point 335b, so as to output a first screen 35a on the display; Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Regarding claim 6, Singh as modified by Venkatesan and Sin discloses the APU of claim 4, wherein one of the two EDPA interfaces coupled to the display is configured to sync operations order between at least one of the at least one EDPA and the display,
wherein while the at least one EDPA sending processed image data to a display buffer, the one EDPA interface coupled to the display informs the display, and then the display is enabled to read and display the processed image data and raw image data (Sin’s paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260; paragraph [0100]: a display driver integrated circuit (e.g., the display driver integrated circuit 261 of FIG. 2) included in the display may read the first frame 33a stored in the buffer memory at a time point obtained by adding an offset 337 to a first time point 335a of the second synchronization period and at a time point obtained by adding the offset 337 to a second time point 335b, so as to output a first screen 35a on the display; Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, and further in view of Mody U.S. Patent Application 20200210351.
Regarding claim 7, Singh as modified by Venkatesan discloses upon determining that the plurality of hosts comprise at least one DLA, at least one of the plurality of EDPA interfaces is configured as a buffer controller used to control operations, between the at least one DLA and the at least one EDPA of at least one buffer (Singh’s paragraph [0188]: The scalar constants A, B, C, 710C may include values stored in memory, buffers, registers, or some other repository… The scalar constants 710C may be provided into the deep learning accelerator 700 in any desirable relationship with the streaming data X, Y, provided at first and second stream inputs 702, 702, respectively, and with vector constant data provided at vector constant inputs A, B, C, 706A, 706B, 706C). However, Singh as modified by Venkatesan fails to disclose circular buffer controller (CBFC) used to control operations.
Mody discloses circular buffer controller (CBFC) used to control operations (paragraph [0005]: transfer image data via circular buffers formed in the shared memory, to process the image data to produce processed image data, and to store the processed image data in one of the circular buffers. The common DMA controller is coupled to the shared memory, and is configured to transfer data between memory external to the image processing accelerator and one or more of the circular buffers).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to use circular buffer as taught by Mody, to reduce time and power needed to process a video stream.
Claim 10-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, and further in view of Zhao U.S. Patent Application 20220214903.
Regarding claim 10, Singh as modified by Venkatesan discloses plurality of EDPA interfaces (Singh's paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated). However, Singh as modified by Venkatesan fails to disclose upon determining a number of VM, interfaces are configured to couple the number of VM, and the corresponding number of interface is identical to the number of VM.
Zhao discloses upon determining a number of VM, interfaces are configured to couple the number of VM, and the corresponding number of interface is identical to the number of VM (paragraph [0075]: Driver 404 can include one or more function libraries and application programming interfaces (API's) that enable the VM 402 containing the driver 404 to communicate with one or more artificial intelligence (AI) accelerators 410 that are communicatively coupled with the VM 402 via hypervisor 405, CPU 406, and bus 407; see fig. 4A).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to use virtual machine as taught by Zhao, to migrate a virtual machine that uses the artificial accelerator.
Regarding claim 11, Singh discloses a method for virtual hardware interface, comprising:
a plurality of hosts of an APU (paragraph [0002]: Learning machines discussed in this disclosure may fall under the technological titles of machine learning, artificial intelligence, neural networks, probabilistic inference engines, accelerators, and the like);
configuring a corresponding number of EDPA interfaces of the APU for optionally coupling the plurality of hosts according to the plurality of hosts (paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; see fig. 3 and fig. 4 configurable accelerator framework (CAF) 400); and
coupling at least one EDPA of the APU to the EDPA interfaces (paragraph [0120]: Multiple accelerators, grouped or chained together, handle varying sizes for feature maps data and multiple kernels in parallel. Grouping the convolutional accelerators (CA's) 600 to achieve larger computational entities enables choosing an acceptably optimal balancing of the available data bandwidth, budget power, and available processing resources; see fig. 4 configurable accelerator framework (CAF) 400),
wherein the EDPA interfaces are configured as interfaces between the plurality of hosts and the at least one EDPA (paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a (interfaces between external hosts and accelerators 600), a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c (interfaces between ISP hosts and accelerators 600). Other interfaces are also contemplated; see fig. 3 and fig. 4 configurable accelerator framework (CAF) 400).
Singh discloses all the features with respect to claim 11 as outlined above. However, Singh fails to disclose identifying the number and types of a plurality of hosts, the number of the plurality of EDPA interfaces is more than the number of the at least one EDPA explicitly.
Venkatesan discloses the number of the plurality of EDPA interfaces is more than the number of the at least one EDPA (col. 5 line 24-29: the AI accelerator 110 may include more than one interface controller 150. Further, functionality attributed to a component of the AI accelerator 110 may be accomplished by a different component included in the AI accelerator 110, by the cache allocation module 120, or by a different system; col. 8 line 61-64: the interface controller 150 may be a network interface controller that can allow communication among the cores on the same network using cables or wirelessly; each AI accelerator has plurality of interfaces both internal and external).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh’s to use multiple interfaces as taught by Venkatesan, to dynamic cache allocation in AI accelerators.
Singh as modified by Venkatesan discloses all the features with respect to claim 11 as outlined above. However, Singh as modified by Venkatesan fails to disclose identifying the number and types of a plurality of hosts.
Zhao discloses identifying the number and types of a plurality of hosts (paragraph [0079]: Checkpoint 420 is a snapshot of a state of VM1-S, up to and including the virtual function 411 (e.g. VF1) that is being migrated as a part of the migration of VM1-S from HOST-S 401 to HOST-T 451; see table "Exemplary Contents of a Checkpoint Frame 420" after paragraph [0079], Cluster 310 AI Accelerators 105 Number and type (mfr./model) allocated).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan’s to identify number and types of host as taught by Zhao, to migrate a virtual machine that uses the artificial accelerator.
Regarding claim 12, Singh as modified by Venkatesan and Zhao discloses the method of claim 11, wherein the types of the plurality of hosts include at least one of an image signal processor (ISP), a display, a deep learning accelerator (DLA), a vision processing unit (VPU), and a virtual machine (VM) (Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh’s to use multiple interfaces as taught by Venkatesan, to dynamic cache allocation in AI accelerators; and combine Singh and Venkatesan’s to identify number and types of host as taught by Zhao, to migrate a virtual machine that uses the artificial accelerator.
Claim 20 recites the functions of the apparatus recited in claim 10 as method steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 10 applies to the method steps of claim 20.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, in view of Zhao U.S. Patent Application 20220214903, and further in view of Zhao U.S. Patent Application 20240354367.
Regarding claim 13, Singh as modified by Venkatesan and Zhao discloses plurality of EDPA interfaces (Singh's paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated). However, Singh as modified by Venkatesan and Zhao fails to disclose upon determining that the type of the plurality of hosts comprise at least one VPU, the at least one of the interfaces is configured as a register used to store instructions accessible by the at least one VPU for controlling at least one of the at least one EDPA.
Zhao discloses upon determining that type of the plurality of hosts comprise at least one VPU, at least one of the interfaces is configured as a register used to store instructions accessible by the at least one VPU for controlling at least one of the at least one EDPA (paragraph [0041]: The data is then transferred from the “global memory” to a shared memory and/or register(s) of the graphics processor 132, VPU 138 and/or AI accelerator 148).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh, Venkatesan and Zhao’s to use register as taught by Zhao, to load data based on an order of operations associated with the data.
Claim 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, in view of Zhao U.S. Patent Application 20220214903, and further in view of Sin U.S. Patent Application 20210225320.
Regarding claim 14, Singh as modified by Venkatesan and Zhao discloses upon determining that the plurality of hosts comprise an ISP and a display, two EDPA interfaces of the plurality of EDPA interfaces are configured respectively coupled to the ISP and the display (Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources). However, Singh as modified by Venkatesan and Zhao fails to disclose two interfaces of the plurality of interfaces are configured as hardware sync engines (HSEs) explicitly.
Sin discloses two interfaces of the plurality of interfaces are configured as hardware sync engines (HSEs) (paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh and Venkatesan and Zhao’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Regarding claim 15, Singh as modified by Venkatesan, Zhao and Sin discloses the method of claim 14, wherein one of the two EDPA interfaces coupled to the ISP is configured to sync operations order between the ISP and at least one of the at least one EDPA,
wherein while the ISP sending raw image data to a DRAM buffer, the one EDPA interface coupled to the ISP informs the at least one of the at least one EDPA, and then the at least one of the at least one EDPA is enabled to read the raw image data from the DRAM buffer (Sin’s paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260; paragraph [0100]: a display driver integrated circuit (e.g., the display driver integrated circuit 261 of FIG. 2) included in the display may read the first frame 33a stored in the buffer memory at a time point obtained by adding an offset 337 to a first time point 335a of the second synchronization period and at a time point obtained by adding the offset 337 to a second time point 335b, so as to output a first screen 35a on the display; Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh, Venkatesan and Zhao’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Regarding claim 16, Singh as modified by Venkatesan, Zhao and Sin discloses the method of claim 14, wherein one of the two EDPA interfaces coupled to the display is configured to sync operations order between at least one of the at least one EDPA and the display,
wherein while the at least one EDPA sending processed image data to a display buffer, the one EDPA interface coupled to the display informs the display, and then the display is enabled to read and display the processed image data and raw image data (Sin’s paragraph [0054]: the first synchronization signal may be software vertical-sync (SW Vsync) for enabling a graphic processing device (e.g., a graphic processor unit (GPU) and an image signal processor (ISP)) to refresh a frame buffer, and the second synchronization signal may be hardware vertical-sync (HW Vsync) for refreshing a screen of the display 260; paragraph [0100]: a display driver integrated circuit (e.g., the display driver integrated circuit 261 of FIG. 2) included in the display may read the first frame 33a stored in the buffer memory at a time point obtained by adding an offset 337 to a first time point 335a of the second synchronization period and at a time point obtained by adding the offset 337 to a second time point 335b, so as to output a first screen 35a on the display; Singh’s paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a, a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c. Other interfaces are also contemplated; paragraph [0156]: Data passed from the data switch 506 may, in some cases, pass through one or more optional output synchronization logic stages 514… Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh, Venkatesan and Zhao’s to sync hardware as taught by Sin, to respond to user's interaction promptly.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Singh U.S. Patent Application 20230153621 in view of Venkatesan U.S. Patent 12475054, in view of Zhao U.S. Patent Application 20220214903, and further in view of Mody U.S. Patent Application 20200210351.
Regarding claim 17, Singh as modified by Venkatesan and Zhao discloses upon determining that the type of the plurality of hosts comprise at least one DLA, at least one of the plurality of EDPA interfaces is configured as a buffer controller used to control operations, between the at least one DLA and the at least one EDPA of at least one buffer (Singh’s paragraph [0188]: The scalar constants A, B, C, 710C may include values stored in memory, buffers, registers, or some other repository… The scalar constants 710C may be provided into the deep learning accelerator 700 in any desirable relationship with the streaming data X, Y, provided at first and second stream inputs 702, 702, respectively, and with vector constant data provided at vector constant inputs A, B, C, 706A, 706B, 706C). However, Singh as modified by Venkatesan and Zhao fails to disclose circular buffer controller (CBFC) used to control operations.
Mody discloses circular buffer controller (CBFC) used to control operations (paragraph [0005]: transfer image data via circular buffers formed in the shared memory, to process the image data to produce processed image data, and to store the processed image data in one of the circular buffers. The common DMA controller is coupled to the shared memory, and is configured to transfer data between memory external to the image processing accelerator and one or more of the circular buffers).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Singh, Venkatesan and Zhao’s to use circular buffer as taught by Mody, to reduce time and power needed to process a video stream.
Allowable Subject Matter
Claim 8-9 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 and 18 are about the at least one DLA is enabled to read information about the circular buffer from the at least one EDPA interface, wherein, when the at least one EPDA writes data into the circular buffer, the DLA is enabled to read the data according to the information of the at least one circular buffer.
Singh 20230153621, Venkatesan 12475054, Zhao 20220214903, and Mody 20200210351 combined cannot teach these features perfectly. These limitations when read in light of the rest of the limitations in the claim and the claims to which it depends make the claim allowable subject matter.
Claim 9 and 19 are about the at least one EDPA is enabled to write data into the circular buffer, until the circular buffer is full, which the at least one EDPA is informed by the at least one EDPA interface, wherein, the DLA is enabled to read the data from the circular buffer until the circular buffer is empty, which the DLA is informed by the at least one EDPA interface.
Singh 20230153621, Venkatesan 12475054, Zhao 20220214903, and Mody 20200210351 combined cannot teach these features perfectly. These limitations when read in light of the rest of the limitations in the claim and the claims to which it depends make the claim allowable subject matter.
Response to Arguments
Applicant's arguments filed 9/9/2026, page 8 - 12, with respect to the rejection(s) of claim(s) 1 and 11 under 103, have been fully considered but they are not persuasive. (FP 7.37)
Applicant argues on page 8-12 that Venkatesan does not disclose or suggest that interface controller 150 is an external EDPA interface configured between a plurality of hosts and at least one EDPA. Nor does Venkatesan disclose or suggest that the number of such host-to-EDPA interfaces exceeds the number of EDPAs", and “Singh's external device interfaces are associated with external devices, such as a digital visual interface and image sensor/ISP interfaces. The cited disclosure does not teach or suggest that those interfaces are configured between a plurality of hosts and at least one EDPA, nor that the number of such host-to-EDPA interfaces is greater than the number of EDPAs.
In reply, the rejection is based on Singh and Venkatesan combined. Singh discloses the plurality of EDPA interfaces are configured as interfaces between the plurality of hosts and the at least one EDPA (paragraph [0132]: external device interface 408 includes a digital visual interface (DVI) external device interface 408a (interfaces between external hosts and accelerators 600), a first image sensor interface and image signal processor (ISP) external device interface 408b, and a second image sensor interface and ISP external device interface 408c (interfaces between ISP hosts and accelerators 600). Other interfaces are also contemplated; see fig. 3 and fig. 4 configurable accelerator framework (CAF) 400). In fact, Singh discloses interfaces 408a, 408b, 408c and other interfaces, Singh’s number of interfaces is greater than the number of accelerators 600.
Venkatesan discloses the number of the plurality of EDPA interfaces is more than the number of the at least one EDPA (col. 5 line 24-29: the AI accelerator 110 may include more than one interface controller 150. Further, functionality attributed to a component of the AI accelerator 110 may be accomplished by a different component included in the AI accelerator 110, by the cache allocation module 120, or by a different system; col. 8 line 61-64: the interface controller 150 may be a network interface controller that can allow communication among the cores on the same network using cables or wirelessly; each AI accelerator has plurality of interfaces both internal and external). Venkatesan also discloses interface controller 150 controls different system, communicates using cables or wirelessly.
Furthermore, claim 1 and 11 don’t limit the interfaces are external interface only, the argument is not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/YI YANG/
Primary Examiner, Art Unit 2616
Prosecution Insights