DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 12/02/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 24 is objected to because of the following informalities:
Regarding claim 24, in L1, amend phrase “a switching power supply” to – “the switching power supply”— (Note that in claim 1, in L1-2, Applicant already claimed “a switching power supply”. Appropriate correction is required to avoid 112(b) issues). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 11, 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nate (US Pub 2018/0026523).
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Above Fig. 4-6, from Nate (US Pub 2018/0026523)
Regarding independent claim 1, Nate teaches (Fig. 4-8; Para 71-96, 105-120) a control circuit (i.e., control circuit “ctrl” being combined operation of ‘10-30, D2, C02, C2-3’; wherein 10 includes start-up circuit 101; taught ctrl shares similar controlled features throughout Fig. 1-8; wherein collective details cited in para 84-85, 88-112. Note that Nate teaches other controllers such as, 53 or 62 as well.), which has a high-voltage startup function (i.e., 101; Para 84-85, 88-112) and is applied to a switching power supply (Fig. 4; switching power supply (SPS) using flyback converter; Para 75 (overall detail being in para 71-96)), wherein the control circuit (ctrl; para 84-85, 88-112) comprises:
a startup power supply circuit (Fig. 4-6; start up circuit being combined operation of ‘30, SW1, CS1, D3-4’; para 99-112), configured
to provide a first current path (Fig. 4-6; 1st current path I1 vs. 2nd current path I1b, using two parallel connected switching operation in 101; Para 99-112)
under an active state of the startup power supply circuit (Fig. 4-6; at time t0-t1, during startup stage, such as, when Vdc starts rising influencing Vcc to rise, prior to use of 101, since it is evident that none of Vdc or Vcc has reached stabilized state yet, using manipulated path of I1 vs. I1b; para 99-112);
a power control circuit (CMP1-2), configured
to provide a second current path (Fig. 4-6; 1st current path I1 vs. 2nd current path I1b, using two parallel connected switching operation in 101; Para 99-112)
under an active state of the power control circuit (Fig. 4-6; at time t1-t2, when Vdc is stable and on, influencing Vcc to still rise but in an unstable way, requiring use of 101, to detect stable Vcc output so that M1’s switching operation can begin for performing conversion, using manipulated path of I1 vs. I1b; para 99-112); and
a high-voltage switch device (M2), which is
coupled to a high-voltage node (VH, Vcc) in a power supply loop of the switching power supply (Fig. 4), and
configured
to implement charging startup of the control circuit (charging up of Vcc for 10) through the first current path in a startup stage (a startup stage t0-t2, rising but unstable Vcc, thus requiring 101’s operation to manipulate paths I1 vs. I1B), and
to implement power conversion of the switching power supply (switching of M1) through the second current path after startup is completed (after a startup is completed, being at and after time t2, when Vcc is up and stabilized to start switching of M1 for performing the conversion).
Regarding claim 7, Nate teaches the startup power supply circuit (Fig. 4-6; start up circuit being combined operation of ‘30, SW1, CS1, D3-4’; para 99-112) comprises:
a diode (D3) arranged on the first current path (Fig. 4-6; 1st current path I1 vs. 2nd current path I1b, using two parallel connected switching operation in 101; Para 99-112),
wherein
an anode of the diode (D3’s anode) is coupled to a source electrode of the high-voltage switch device (NMOS M2’s source coupling D3’s anode), and
the cathode of the diode (D3’s cathode) is coupled to the power supply terminal of the control circuit (Vcc of 10 coupling D3’s cathode).
Regarding claim 11, Nate teaches the startup power supply circuit further (Fig. 4-6; start up circuit being combined operation of ‘30, SW1, CS1, D3-4’; para 99-112) comprises a current limiter (operation of ‘SW1, CS1’ configured to limit current Ilmt) arranged on the first current path (Fig. 4-6; 1st current path I1 vs. 2nd current path I1b, using two parallel connected switching operation in 101; Para 99-112).
Regarding claim 24, Nate teaches a switching power supply (Fig. 4; switching power supply (SPS) using flyback converter; Para 75 (overall detail being in para 71-96)), comprising: a transformer (T1) which comprises a primary winding (N1) and a secondary winding (N2); and the control circuit (ctrl) according to claim 1, connected to the primary winding (N1).
Claims 1, 3-5, 11, 14, 20, 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leuders et al. (“Ref 608”, US Pat 11621708).
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Above amended Fig. 11, 1, 8, from Leuders et al. (“Ref 608”, US Pat 11621708)
Regarding independent claim 1, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) a control circuit (control circuit “ctrl” being combined operation of 1140 Active Clamp Feedback (ACF) controller, startup circuit 100, driver 1120 and SR controller 1130), which has a high-voltage startup function (i.e., 100 details being in Fig. 1) and is applied to a switching power supply (1100 Flyback converter), wherein the control circuit (ctrl) comprises:
a startup power supply circuit (pre-charge circuit 122’s output used to drive 101’s switch), configured to provide a first current path under an active state of the startup power supply circuit (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1);
a power control circuit (112, 126, 114), configured to provide a second current path (various reduced current control between nodes ‘124, 106 and 108’, in order to make sure required Vaux is provided as output) under an active state of the power control circuit (required switching operation in ‘112, 126, 114’); and
a high-voltage switch device (101), which is coupled to a high-voltage node (high-voltage node being both Vsw, Vaux; wherein Vaux is then sensed and provided as Vdd for powering the ctrl) in a power supply loop of the switching power supply, and configured
to implement charging startup of the control circuit (i.e., when Vdd is about to start up or rising to power up ctrl; wherein note that Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation) through the first current path in a startup stage, and
to implement power conversion of the switching power supply (i.e., when Vdd is completely started up for ctrl and performing the conversion by switching 1114 or 1108; wherein note that Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation) through the second current path after startup is completed.
Regarding claim 3, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) wherein the control circuit (control circuit “ctrl” being combined operation of 1140 Active Clamp Feedback (ACF) controller, startup circuit 100, driver 1120 and SR controller 1130) further comprises: a multiplexing control circuit (i.e., 118), which is used to monitor a voltage at a power supply terminal of the control circuit (i.e., Vaux from 108) so as to obtain a determination result (Vsd) by determining a startup status of the control circuit (Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation; Vaux is monitored by 118; wherein 118 compares Vaux with Vref, provides a comparison result being a control signal Vsd to switch ‘Q5-6’ on/off, as required, which adjusts gate voltage of Q3 & Q1, respectively, ultimately adjusting output current value of Q1 to output required Vaux back to the ctrl), and output a control signal (Vsd) according to the determination result (i.e., Vaux is determined using 118) so as to enable (i.e., using feedback operation of Fig. 1) one of the startup power supply circuit (pre-charge circuit 122’s output used to drive 101’s switch) and the power control circuit (112, 126, 114) (Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation; Vaux is monitored by 118; wherein 118 compares Vaux with Vref, provides a comparison result being a control signal Vsd to switch ‘Q5-6’ on/off, as required, which adjusts gate voltage of Q3 & Q1, respectively, ultimately adjusting output current value of Q1 to output required Vaux back to the ctrl).
Regarding claim 4 (similar to claims 3 and 5), Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) the multiplexing control circuit is configured to: when the voltage at the power supply terminal (Vaux) is lower than a power supply threshold voltage (Vref), enable the startup power supply circuit to match the first current path for the high-voltage switch device (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1), and when the voltage at the power supply terminal reaches the power supply threshold voltage, enable the power control circuit to match (i.e., when Q5, Q6 needs to be switched on) the second current path (various reduced current control between nodes ‘124, 106 and 108’, in order to make sure required Vaux is provided as output) for the high-voltage switch device (Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation; Vaux is monitored by 118; wherein 118 compares Vaux with Vref, provides a comparison result being a control signal Vsd to switch ‘Q5-6’ on/off, as required, which adjusts gate voltage of Q3 & Q1, respectively, ultimately adjusting output current value of Q1 to output required Vaux back to the ctrl).
Regarding claim 5 (similar to claims 3-4), Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) the multiplexing control circuit (i.e., 118) comprises: a comparison circuit (i.e., 118), wherein a first input terminal of the comparison circuit receives the voltage at the power supply terminal (i.e., Vaux from 108), a second input terminal of the comparison circuit receives a power supply threshold voltage (Vref), and the comparison circuit is configured to obtain a comparison result by comparing the voltage at the power supply terminal with the power supply threshold voltage, and output the control signal (Vsd) according to the comparison result (Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation; Vaux is monitored by 118; wherein 118 compares Vaux with Vref, provides a comparison result being a control signal Vsd to switch ‘Q5-6’ on/off, as required, which adjusts gate voltage of Q3 & Q1, respectively, ultimately adjusting output current value of Q1 to output required Vaux back to the ctrl), and the control signal (Vsd) is used to enable (i.e., using feedback operation of Fig. 1) one of the startup power supply circuit (pre-charge circuit 122’s output used to drive 101’s switch) and the power control circuit to be operated in the active state (112, 126, 114) (Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation; Vaux is monitored by 118; wherein 118 compares Vaux with Vref, provides a comparison result being a control signal Vsd to switch ‘Q5-6’ on/off, as required, which adjusts gate voltage of Q3 & Q1, respectively, ultimately adjusting output current value of Q1 to output required Vaux back to the ctrl).
Regarding claim 11, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) the startup power supply circuit (pre-charge circuit 122’s output used to drive 101’s switch) further comprises a current limiter (i.e., since 112 & 126 switching operation can be used to control current for Q3 of 122) arranged on the first current path (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1).
Regarding claim 14, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) wherein the power control circuit (112, 126, 114) comprises:
a second transistor (Q5 and/or Q6 to be periodically on or off, as required, based on 118’s output) arranged on the second current path (various reduced current control between nodes ‘124, 106 and 108’, in order to make sure required Vaux is provided as output), wherein the second transistor is a low-voltage device (use of GaN for 101 and/or any one of switches in Fig. 1 to perform as a low-voltage device; col. 1 L16-35, col. 3 L40-41, col. 6 L9-18 and claim 13); and
a driving controller (118), which is coupled to the gate electrode of the second transistor (Q5 and/or Q6), and configured to provide a driving control signal (Vsd) to control the second transistor to be periodically turned on and off (Q5 and/or Q6 to be periodically on or off, as required, based on 118’s output), so as to implement the power conversion of the switching power supply (Vdd when ctrl is completely started up and performing the conversion by switching 1114 or 1108).
Regarding claim 20, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) the high-voltage switch device is a gallium nitride transistor (use of GaN for 101 and/or any one of switches in Fig. 1; col. 1 L16-35, col. 3 L40-41, col. 6 L9-18 and claim 13).
Regarding claim 24, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) a switching power supply (Fig. 11), comprising: a transformer (1110) which comprises a primary winding (1111) and a secondary winding (1112); and the control circuit (ctrl) according to claim 1, connected to the primary winding (1111 connects ctrl’s ‘100, 1120 & ACF controller, wherein ctrl’s ‘1130, 1132’ is connected to 1112).
Allowable Subject Matter
Claims 2, 6, 8-10, 12-13, 15-19, 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Nate teaches the power control circuit (CMP1-2) controlling a second switch (SW1 vs. CS1) arranged on the second current path (Fig. 4-6; 1st current path I1 vs. 2nd current path I1b, using two parallel connected switching operation in 101; Para 99-112), …to be periodically turned on and off, so as to implement the power conversion of the switching power supply.
However, Wang (US Pub 2021/0184584) teaches (Fig. 3; Para 41-42 and 25-37) the power control circuit (600a) comprises: a second transistor (J1) arranged on the second current path (current source IS formed using transistors J1-2 & R1, wherein Wang’s IS similar to Nate’s CS, J1-2 anticipated to be periodically to be turned on/off; wherein Wang’s power control circuit provides two different Vcc based on following conditions: i) when Vcc<Vth in 620a, current source IS being switched on from off, but 601 is switched off, leads to respective stored energized current from auxiliary winding a1 being transferred to C22 for providing one kind of Vcc vs. ii) when Vcc>Vth in 620a, current source IS being switched off, but 601 is switched on from off, providing another kind of Vcc based on respective current), the second transistor being a low-voltage device (J1) and configured to be operated in an off state during the different stages of the control circuit (i.e., as different Vcc required by control circuit 420 for performing switching conversion, using SW1-2) (current source IS formed using transistors J1-2 & R1, wherein Wang’s IS similar to Nate’s CS, J1-2 anticipated to be periodically to be turned on/off; wherein Wang’s power control circuit provides two different Vcc based on following conditions: i) when Vcc<Vth in 620a, current source IS being switched on from off, but 601 is switched off, leads to respective stored energized current from auxiliary winding a1 being transferred to C22 for providing one kind of Vcc vs. ii) when Vcc>Vth in 620a, current source IS being switched off, but 601 is switched on from off, providing another kind of Vcc based on respective current).
However, Ref 608 teaches (Fig. 11, wherein annotated Fig. 1 shows detail of 100 and part of Fig. 4 shows part of ACF controller (i.e., 430 and 432)) wherein the power control circuit (112, 126, 114) comprises: a second transistor (any one of selected transistor can be selected as a second transistor in taught power control circuit ‘112, 126, 114’; wherein, use of GaN for 101 and/or any one of switches in Fig. 1 to perform as a low-voltage device; col. 1 L16-35, col. 3 L40-41, col. 6 L9-18 and claim 13) arranged on the second current path (wherein, each switching operation within the power control circuit is designed to reduce or adjust various current path control between nodes ‘124, 106 and 108’, in order to make sure required Vaux is provided as output, which is used to power up ctrl), the second transistor being a low-voltage device and configured to be operated in an off state (i.e., when selected 2nd transistor being off) during the startup stage (i.e., when Vdd is about to start up or rising to power up ctrl; wherein note that Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation) and operated in an enable state (i.e., when selected 2nd transistor being on) after the startup is completed (i.e., when Vdd is completely started up for ctrl and performing the conversion by switching 1114 or 1108; wherein note that Vdd is based on sensed Vs, which is based on ‘Vaux, 430 & 432’ combined operation), wherein the power control circuit (112, 126, 114) is operated … when the second transistor is in the off state, and the power control circuit (112, 126, 114) is operated … when the second transistor is in the enable state.
However, none of the arts alone &/or in combination teaches, nor would it be obvious to piecewise combine with any other arts to teach the following limitation(s), “the power control circuit (additionally) comprises: a second transistor (isolated from power supply circuit and high voltage switch device) arranged on the second current path, the second transistor configured to be operated in an off state during the startup stage and operated in an enable state after the startup is completed, wherein the power control circuit is operated in an inactive state when the second transistor is in the off state, and the power control circuit is operated in an active state when the second transistor is in the enable state”, as claimed in claim 2.
Claims 12-13, 15-16, 21-23 depend on claim 2.
Regarding claim 6, Ref 608 teaches the startup power supply circuit (pre-charge circuit 122’s output used to drive 101’s switch) comprises: a first transistor arranged on the first current path (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1), the first transistor being a low-voltage device (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1; wherein use of GaN for 101 and/or any one of switches in Fig. 1 to perform as a low-voltage device; col. 1 L16-35, col. 3 L40-41, col. 6 L9-18 and claim 13) and configured to be operated in an on state during the startup stage (Q3=on during a startup stage, where Vdd needs to be increased to power up to activate ctrl, which is still not active) and to be operated in an off state after the startup is completed (Q3=off, switching off Q1, once startup is complete, meaning required Vdd is already done and ctrl is up is activated), wherein the active state and an inactive state of the startup power supply circuit is switched in accordance with a switching operation between the on state and the off state of the first transistor; and a diode (Daux) arranged on the first current path (i.e., when pre-charge circuit 122’s Q3=on, and its output is used to drive 101’s switch to provide 1ST current path IQ1), wherein an anode of the diode (Daux’s anode) is coupled to a drain electrode of the first transistor (i.e., Q3’s drain, via other elements).
However, cited art(s) failed to teach, as whole, following italicized diode’s relationship with the taught first transistor in the startup power supply circuit (meaning if Applicant selects to use this claim to amend for allowability Examiner recommend the Applicant to consider whole claim and not just diode portion) in such a way that “a first transistor arranged on the first current path, the first transistor being a low-voltage device and configured to be operated in an on state during the startup stage and to be operated in an off state after the startup is completed, wherein the active state and an inactive state of the startup power supply circuit is switched in accordance with a switching operation between the on state and the off state of the first transistor; and a diode arranged on the first current path, wherein an anode of the diode is coupled to a drain electrode of the first transistor, and a cathode of the diode is coupled to the power supply terminal”.
Claims 8-10, 17-19 depend on claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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Above excerpt from Tushar (DE 10 2014 107815)
Tushar (DE 10 2014 107815) teaches (Fig. 8b; Q2; Para 54) interchangeable use between a gallium nitride transistor and any other type of transistor.
Lin (US Pub 2009/0073725) teaches startup circuit (Fig. 4) includes clamping circuit 210, current limit circuit (214), comparator (216).
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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