Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkner et al. (hereinafter Jenkner, US Pat No. 9,525,339) in view of Johnson et al. (hereinafter Johnson, US Pat No. 6,483,728).
Regarding claim 1, Jenkner disclosed a sensor component comprising:
a housing (inherent of Jenkner);
an electrical interface (inherent of Jenkner because for it to connect to exterior) disposed on an exterior of the housing);
a capacitive transducer (MEMS microphone 306) disposed in the housing, the capacitive transducer including a first electrode and a second electrode;
and an electrical circuit (Figs. 1-4) disposed in the housing and electrically coupled to the capacitive transducer (MEMS microphone 306) and the electrical interface, the electrical circuit including a bias voltage source (col. 2, line 60 to col. 3, line 6, col. 3, lines 42-51, col. 5, lines 4-58, etc.) coupled to the first electrode, the bias voltage source comprising: a charge pump (e.g., 102, 302, 402) including a clock input (CLK); a reference voltage source (col. 3, line 31-41, col. 4, lines 1- 38, col. 4, line 63- 57, and Figs. 6-10) that provides a reference voltage; a clock circuit (410, 510 or 910) that outputs a clock signal with a clock voltage; and a voltage booster circuit (Fig. 8, 202, 502a to 502N of Fig. 5a, 902 of Fig. 2) coupled to the charge pump and coupled to the reference voltage source.
While Jenkner fails to disclose, Johnson teaches wherein the voltage booster circuit (Fig. 2 or Fig. 4) receives the reference voltage (VR or VDD) and the clock signal (CLK or
C
L
K
-
) increases the reference voltage (e.g., 2VR, 4 VR or 8VR, etc.), and increases a voltage of the clock signal (e.g., by 147 or 148, col. 4, lines 41-45) provided to the charge pump clock input based on the increased reference voltage (col. 4, lines 41-45).
As both Jenkner and Johnson teach voltage booster or multi-pump stages, it would have been obvious to an artisan before the effective filing date of the claimed invention to apply the teaching of Johnson to the device of Jenkner in order to increase the voltage of the clock signal. Furthermore, a finding that one of ordinary skill in the art could have substituted one known element (booster stages of Jenkner) for another (Booster stages of Johnson) would have been an obvious modification of Jenkner, and the results of the substitution would have been predictable.
Regarding claim 2, both Jenkner and Johnson disclosed wherein the charge pump comprises a charge pump input and the voltage booster circuit provides the increased reference voltage to the charge pump input (See Figs. 104, and 709 of Jenkner or Figs. 2 and 4 of Johnson).
Regarding claim 3, the combination of Jenkner and Johnson disclosed wherein the
voltage booster circuit comprises a plurality of voltage booster stages, where a first voltage
booster stage increases a clock voltage provided to a second voltage booster stage (see Figs. 2
and 4 of Johnson).
Regarding claim 4, the combination of Jenkner and Johnson disclosed wherein the first
voltage booster stage (132 of Johnson) increases the reference voltage and provides the
increased reference voltage (2VR) to the second voltage booster stage (134 of Johnson, also see
Figs. 5a, 8 and 9 of Jenkner) .
Regarding claim 5, the combination of Jenkner and Johnson disclosed, wherein the
voltage booster circuit comprises a voltage level shifter (212, 222 or Fig. 8 of Johnson) coupled
to an output of the first voltage booster stage and coupled to a clock input of the second
voltage booster stage (Fig. 4 of Johnson), and the voltage level shifter increases the clock
voltage provided to the second voltage booster stage based on an increased reference voltage
output from the first voltage booster stage (col. 6 lines 34-65 of Johnson).
Regarding claims 12, the combination of Jenkner and Johnson disclosed wherein the
voltage booster circuit comprises a first voltage booster capacitor (184) and a second voltage
booster capacitor (186) driven by respective complimentary clock drivers, where the
complimentary clock drivers control charging and discharging of each respective capacitor (Fig.
3 and col. 5, lines 7-23, also see 266 and 268 of Fig. 6).
Regarding claim 13, the combination of Jenkner and Johnson disclosed wherein the
charge pump comprises an output, and wherein the bias voltage source comprises a low pass
filter coupled between the charge pump output and the capacitive transducer (See Fig. 4 and
col. 6, lines 6-18 of Jenkner).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkner et al. (hereinafter Jenkner, US Pat No. 9,525,339) in view of Johnson et al. (hereinafter Johnson, US Pat No. 6,483,728) as applied to claims 1-5, 12 and 13 above and further in view of Lesso et al. (hereinafter Lesso, US Pub. No. 2012/0170770).
While the combination of Jenkner and Johnson fails to disclose, Lesso teaches using a multiplexer that selectively enables a voltage booster output signal provided from at least one voltage booster (e.g., selecting output voltage of the charge pump by altering the multiplexer logic or connection (0307)). Based on this teaching, it would have been obvious to an artisan before the effective filing date of the claimed invention to incorporate multiplexing technique of Lesso into the combination of Jenkner and Johnson in order to allow selective of output from booster stages. In addition, a finding that one of ordinary skill in the art would have recognized that applying the know technique would have yielded predictable results and would have been an obvious modification to the combination of Jenkner and Johnson.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkner et al. (hereinafter Jenkner, US Pat No. 9,525,339) in view of Johnson et al. (hereinafter Johnson, US Pat No. 6,483,728) as applied to claims 1-5, 12 and 13 above and further in view of Carfore (US Pat No. 12,520,085).
Regarding claim 14, the combination of Jenkner and Johnson further disclosed an amplifier (Figs. 2, 3, 8 or 9 of Jenkner). Although the combination does not disclose the amplifier is a non-inverting amplifier, Carfore teaches a non-inverting amplifier (see claim 9) coupled to the capacitive transducer (410). Based on the teaching of Carfore, it would have been obvious to an artisan before the effective filing date of the claimed invention to incorporate such well known amplifier in the combination of Jenkner and Johnson in order to take the advantage feature of non-inverting in reducing noise even with a high input impedance. Regarding to the specific impedance, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 15, the combination of Jenkner and Johnson disclosed all the features of claim 15 (see the rationales as set forth in claim 1 above) except the detail structure of MEMS transducer. However, Carfore teaches such well known MEMS transducer structure (Fig. 1). Fig. 1 of Carefore shows a microelectromechanical systems (MEMS) transducer disposed over the sound port, the MEMS
transducer separating the housing into a front volume acoustically coupled to the sound port
and a back volume on an opposite side of the MEMS transducer from the sound port (Fig. 1).
Based on this teaching, it would have been obvious to an artisan before the effective filing date
of the claimed invention to incorporate such well known MEMS transduce of Carefore into the ‘
combination of Jenkner and Carfore for the purpose of generating sound or having compact package. Furthermore, a finding that one of ordinary skill in the art could have substituted one known element (MEMS transduce of Jenkner) for another (MEMS transduce of Carfore) would have been an obvious modification of Jenkner, and the results of the substitution would have been predictable.
Regarding claim 16, the combination of Jenkner, Johnson and Carfore disclosed wherein the voltage booster circuit comprises a plurality of voltage booster stages (132-136 of Johnson or 202, 902, 5.02 of Jenkner), where a first voltage booster stage increases a clock voltage provided to a second voltage booster stage, and wherein the first voltage booster stage increases the reference voltage and provides the increased reference voltage to the second voltage booster stage (col. 4, lines 14-47 of Johnson.
Claims 7-11, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 7, 17 and 19, the prior art does not disclose “ wherein the voltage booster circuit comprises: at least two transistors, each transistor including a gate and a source; and a switch control circuit coupled between the gates of the at least two transistors, where the switch control circuit controls the at least two transistors independent of the reference voltage” in combination with all limitation recited in the independent claims.
Claims 8-11, 18 and 20 are allowed because they are depending on allowable claims 7, 17 and 19 respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US2014/0079254 to Kim et al. is cited to shows a sensor device with MEMS microphone, voltage booster, reference voltage, and bias circuit (see Fig. 1).
US 2023/0303388 to ITOYAMA et al. is cited to show a sensor device comprising a MEMS microphone, a bias circuit, a clock circuit, and a plurality of pump stages.
GB 2563461 to Khenkin et al. is cited to show a MEMS transducer housing structure (See Figs. 2, 3 and 7-8).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON CHAN whose telephone number is (571)272-3022. The examiner can normally be reached on 9AM – 5:30PM from Monday to Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Beck, can be reached at telephone number 571-272-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the USPTO patent electronic filing system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice.
/JASON CHAN/Supervisory Patent Examiner, Art Unit 2619
Prosecution Insights