Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 3A: 362; FIG. 4A: 362. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “a first PMOS transistor having a source connected to a voltage supply”, “a source connected to a reference potential”, “a second PMOS transistor having a source connected to the voltage supply”, “a gate…having a source”, “a third PMOS transistor having a source connected to the source of the source NMOS transistor”. This language makes it unclear as to whether any of the instances of “a source” refer to the same “source” or if each instance of “source” is intended to refer to a different source, in which each instance should be specified as a separate “source” (for example, “first source”, “second source”, “third source”, etc.), or by some other means of distinguishing each “source” from one another.
This language set forth in the claim makes it unclear to one of ordinary skill in the art how to make and/or use the invention. Appropriate correction is required.
Claims 2-7 are rejected as dependent upon claim 1.
Claim 1 sets forth multiple instances of “a reference potential”. Clarification is required to determine if each instance of “a reference potential” is intended to refer to the same instance of “a reference potential” or separate “reference potentials”. Appropriate clarification is required.
Claims 2-7 are rejected as dependent upon claim 1.
Claim 1 sets forth multiple instances of “a first terminal”. Clarification is required to determine if each instance of “a first terminal” is intended to refer to the same instance of “a first terminal” or separate “first terminals”. Appropriate clarification is required.
Claims 2-7 are rejected as dependent upon claim 1.
Claim 1 sets forth multiple instances of “a second terminal”. Clarification is required to determine if each instance of “a second terminal” is intended to refer to the same instance of “a second terminal” or separate “second terminals”. Appropriate clarification is required.
Claims 2-7 are rejected as dependent upon claim 1.
Claim 1 sets forth “a gate connected to the second storage node”, “ a gate connected to the second storage node”, “a gate connected to the first storage node”, “a gate connected to the first storage node”, “a gate connected to the write word line”, “a gate connected to a read word line”, and “a gate connected to the first storage node”.
This language makes it unclear as to whether any of the instances of “a gate” refer to the same “gate” or if each instance of “gate” is intended to refer to a different gate, in which each instance should be specified as a separate “gate” (for example, “first gate”, “second gate”, “third gate”, etc.), or by some other means of distinguishing each “gate” from one another.
This language set forth in the claim makes it unclear to one of ordinary skill in the art how to make and/or use the invention. Appropriate correction is required.
Claims 2-7 are rejected as dependent upon claim 1.
Claim 8 sets forth ‘a source connected to a voltage supply”, “a source connected to the reference potential”, “a source connected to a voltage supply”, “a source connected to the reference potential”.
This language makes it unclear as to whether any of the instances of “a source” refer to the same “source” or if each instance of “source” is intended to refer to a different source, in which each instance should be specified as a separate “source” (for example, “first source”, “second source”, “third source”, etc.), or by some other means of distinguishing each “source” from one another.
This language set forth in the claim makes it unclear to one of ordinary skill in the art how to make and/or use the invention. Appropriate correction is required.
Claims 9-15 are rejected as dependent upon claim 8.
Claim 8 sets forth multiple instances of “a first terminal”. Clarification is required to determine if each instance of “a first terminal” is intended to refer to the same instance of “a first terminal” or separate “first terminals”. Appropriate clarification is required.
Claims 9-15 are rejected as dependent upon claim 8.
Claim 8 sets forth multiple instances of “a second terminal”. Clarification is required to determine if each instance of “a second terminal” is intended to refer to the same instance of “a second terminal” or separate “second terminals”. Appropriate clarification is required.
Claims 9-15 are rejected as dependent upon claim 8.
Claim 9 sets forth “a first PMOS transistor having a source connected to a voltage supply”, “a source connected to a voltage supply”, “a gate connected to the second storage node”, “a gate connected to the second storage node”, etc. This language makes it unclear as to whether any of the instances of “a source” and/or “a gate” refer to the same “source” and/or “gate” or if each instance of “source” and/or “gate” is intended to refer to a different source and/or gate, in which each instance should be specified as a separate “source” and/or “gate” (for example, “first source”, “second source”, “third source”, etc.), (“first gate”, “second gate”, etc.) or by some other means of distinguishing each “source” and/or “gate” from one another.
This language set forth in the claim makes it unclear to one of ordinary skill in the art how to make and/or use the invention. Appropriate correction is required.
Claims 10 and 11 include multiple instances of “a source” and “a gate” which makes it unclear as to whether each instance of “source” and “gate” are intended to refer to the same “source” and/or “gate” or if they are intended to refer to separate instances of the same. Appropriate correction is required.
As applied to claims 1-15, the below art-based rejections are set forth given broad interpretation of the claims in view of indefiniteness issues, and further search and consideration will be required for all claims upon resolution of indefiniteness issues.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 25 sets forth the SRAM integrated circuit of claim 21, further comprising single diffusion block isolating active regions of the SRAM. The term “single diffusion block isolating” and “diffusion block isolating active regions” is not widely recognized in the art or by one of ordinary skill in the art and further clarification is required to understand the term to make and/or use the invention. The specification appears to set forth this term in at least [0024] and [0060], but sufficient description is not provided. Appropriate clarification is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20120275207 A1 (Houston, et al., hereinafter Houston).
Regarding claim 8, Houston teaches a static random access memory (SRAM) circuit comprising: (Houston, “a static random access memory (SRAM)”; FIGS. 1-8) a first storage node (Houston, “first storage node”) and a second storage node; (Houston, “second storage node”) a first and a second inverter cross-coupled at the first and second storage nodes; (Houston, “cross-coupled inverters”; [0020]: “ includes a pair of CMOS inverters consisting of first and second CMOS inverters 105 a, 105 b. The first CMOS inverter 105 a includes first driver and load transistors 110, 115 having a first storage node A that electrically connects a drain D(110) to a drain D(115), as shown”) a first pass gate transistor having a first terminal connected to the first storage node, (Houston, [0022]: “The SRAM cell 100 also includes first and second pass gate transistors 130, 140 that are controlled by a word line WL and are respectively connected between the first storage node A and a first bit line BLT and the second storage node B and a second bit line BLB.”) a second terminal connected to a write bit line and a gate connected to a write word line; (Houston, FIG. 2A-2B; Houston, [0035]: “The SRAM array 200 also includes write circuitry 210 that is connected to a write (only) bit line 220 a and a read/write bit line 220 b, read circuitry 215 that is connected to the read/write bit line 220 b,”) a second pass gate transistor having a first terminal connected to the second storage node, (Houston. [0022]: “second pass gate transistor…”) a second terminal connected to a complementary write bit line and a gate connected to the write wordline; (Houston, FIG. 2A-2B; [0035]), and a read circuit (Houston, [0035]: “read circuitry 215 that is connected to the read/write bit line 220 b,”) having a first terminal connected to a read bit line, (“read/write bit line 220 b”) a second terminal connected to the first storage node, (“first storage node”).
Houston does not appear to explicitly set forth “a third terminal connected to a read word line and a fourth terminal connected to a reference potential.”
However, one of ordinary skill in the art would recognize that this arrangement of “terminals” and the connection to a “reference potential” is merely claiming an obvious modification of elements in space. One of ordinary skill in the art would recognize that the “third terminal connected to a read word line” and “fourth terminal connected to a reference potential” is merely a slightly different configuration of the terminals and read word lines of Houston. (In re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an unexpected, functional, or synergistic result is unpatentable as obvious; In re Rouff, 239 F.2d 919 (C.C.P.A. 1957): Reinforced that relocating known elements for mere convenience, without achieving a new or improved result, is an obvious design choice rather than a patentable invention).
Therefore, although Houston does not explicitly appear to set forth “a third terminal connected to a read word line and a fourth terminal connected to a reference potential”, one of ordinary skill in the art would recognize these terminal connections to these known elements as an obvious modification that does not yield an unexpected, functional, or synergistic result, and therefore is unpatentable as obvious to one of ordinary skill in the art.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20120275207 A1 (Houston, et al., hereinafter Houston) in view of US 6172894 (Hannum).
Regarding claim 12, Houston teaches The SRAM circuit of claim 8, but does not teach wherein the first storage node holds a binary value that is complementary to the binary value held by the second storage node.
Hannum cures the deficiencies of Houston. Hannum teaches wherein the first storage node (Hannum, “pair of storage nodes 110 and 112”) holds a binary value that is complementary to the binary value held by the second storage node. (Hannum, col. 5, lines 47-54: “Latch circuits 106 and 108 respectively include first and second storage nodes 110 and 112 respectively tied to data lines 120 and 122. Each of latches 106 and 108 is a tri-state storage device that can store (1) two complementary bit values (i.e., a one and a zero or a zero and a one)”)
Both Hannum and Houston are directed to memory cells including memory cells with two or more stable states. It would have been obvious to one of ordinary skill in the art to modify the circuit of Houston with the complementary binary values of Hannum with the motivation of adding a functionality to the memory device.
Regarding claim 13, Houston teaches the SRAM circuit of claim 8, but does not appear to teach wherein in a write operation, the write wordline is driven high, causing the first pass gate transistor and the second pass gate transistor to turn ON.
Hannum cures the deficiencies of Houston. Hannum teaches wherein in a write operation, the write wordline is driven high, causing the first pass gate transistor and the second pass gate transistor to turn ON (Hannum, col. 8, lines 1-20: Pulsing word line 168 high during a write cycle of cell 104 causes the source drain paths of pass gate FETs 160-166 to turn ON to cause application of a logic “1” (EV1) high voltage at terminal 147 to nodes 110 and 172 of latches 106 and 108 and a logic “0” (EV2) low voltage at terminal 149 to nodes 112 and 170 of latches 108 and 166.”)
Both Hannum and Houston are directed to memory cells including memory cells with two or more stable states. It would have been obvious to one of ordinary skill in the art to modify the circuit of Houston with the logic high application of Hannum with the motivation of adding a functionality to the memory device.
Claim(s) 16-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220246623 A1 (Hwang, et al., hereinafter Hwang) in view of US 20220115388 A1 (Hirose).
Regarding claim 16, Hwang teaches a static random access memory (SRAM) integrated circuit, (Hwang, FIG. 1-6C; “a static random access memory (SRAM)”) comprising: an upper layer and a lower layer separated by a dielectric layer; (Hwang, [0007]: “The method includes: providing a first metal gate as a first layer; providing a second metal gate as a second layer, the second layer being disposed above the first layer; performing a gate cutting through the first metal gate and the second metal gate; removing a portion of the second metal gate to form a first recess; filling the first recess with a first dielectric material; and providing a cross-couple contact on the second metal gate and a portion of the first dielectric material.”) a plurality of PMOS transistors formed in the upper layer; (Hwang, [0008]: “and two p-type metal oxide semiconductor (PMOS) transistors;”) a voltage supply rail, (Hwang, “voltage source”) a write word line, (Hwang, [0034]: “During the writing operation, for example, if an instruction to write a “1” in the memory cell is to be executed, the word line WL may be set high to turn on the PG1 130 a and the PG2 130 b”) a read bit line and a read word line formed in the upper layer; (Hwang, [0034]: “a value (i.e., “0” or “1”) in the memory cell may be read through a bit line BL”; [0034]: “During the reading operation, a word line WL may be set to high (i.e., logic state “1”) so as to activate access to the memory cell by the PG1 130 a and the PG2 130 b.”) a plurality of NMOS transistors formed in the lower layer, (Hwang, [0008]: “a lower layer including the two NMOS transistors”) wherein the plurality of PMOS transistors are vertically stacked over the plurality of NMOS transistors; (Hwang, [0008]: “a static random access memory (SRAM) cell that includes two n-type metal oxide semiconductor (NMOS) transistors and two p-type metal oxide semiconductor (PMOS) transistors; an upper layer including the two PMOS transistors; a lower layer including the two NMOS transistors; a first shared contact and a second shared contact;”), a ground rail, (FIG. 3).
Hwang does not appear to teach a write bit line and a complementary write bit line formed in the lower layer; and a write word line contact extending from the upper layer into the lower layer to establish contact with a gate of one of the NMOS transistors in the lower layer.
Hirose cures the deficiencies of Hwang. Hirose teaches a write bit line and a complementary write bit line formed in the lower layer; (Hirose, [0024]: “a fifth transistor having one node connected to a first write-bit line, another node connected to the first node, and a gate connected to a write-word line; a sixth transistor having one node connected to a second write-bit line constituting a complementary bit line pair with the first write-bit line, another node connected to the second node, and a gate connected to the write-word line;”) and a write word line contact extending from the upper layer into the lower layer to establish contact with a gate of one of the NMOS transistors in the lower layer. (Hirose, for example, [0095]; “The line 71 is connected to the local interconnect 41i through a contact 91a, and connected to the local interconnect 41l through a contact 91b. The line 72 is connected to the local interconnect 41f through a contact 91c. The line 73 is connected to the local interconnect 41a through a contact 91d. The line 74 is connected to the local interconnect 41h through a contact 91e. The line 75 is connected to the gate line 31 through a contact (gate-contact) 61a, and connected to the line 81 through a contact 91f. The line 76 is connected to the gate line 34 through a contact 61d, and connected to the line 81 through a contact 91g. The line 77 is connected to the gate line 35 through a contact 61e, and connected to the line 82 through a contact 91h. That is, the line 81 is connected to the gate line 31 through the contact 91f, the line 75, and the contact 61c, and connected to the gate line 34 through the contact 91g, the line 76, and the contact 61d. The line 82 is connected to the gate line 35 through the contact 91h, the line 77, and the contact 61e.”)
Hwang and Hirose are both directed to semiconductor storage devices including a P-type FET and an N-type FET which are stacked forming a series of layers. It would have been obvious to one of ordinary skill in the art to combine the teachings of Hwang with the contacts of Hirose in order to teach the limitations set forth in the claim. One of ordinary skill in the art would have the motivation to combine the teachings in order to improve functionality of the semiconductor memory device.
Regarding claim 17, Hwang/Hirose teaches the SRAM integrated circuit of claim 16, wherein the plurality of PMOS transistors include first, second and third PMOS transistors, (Hwang provides for more than two PMOS transistors included in the plurality of transistors: [0037]: “Moreover, the PD1 220 a, the PD2 220 b, the PG1 230 a and the PG2 230 b may be n-type metal-oxide semiconductor (NMOS) transistors, and the PU1 210 a and the PU2 210 b may be a p-type metal-oxide semiconductor (PMOS) transistors. However, the one or more embodiments are not limited thereto, and other transistors and/or other circuit configurations may be used.”); and wherein the plurality of NMOS transistors include first, second, third, fourth and fifth NMOS transistors. (Hwang provides for more than two NMOS transistors included in the plurality of transistors: [0037]: “Moreover, the PD1 220 a, the PD2 220 b, the PG1 230 a and the PG2 230 b may be n-type metal-oxide semiconductor (NMOS) transistors, and the PU1 210 a and the PU2 210 b may be a p-type metal-oxide semiconductor (PMOS) transistors. However, the one or more embodiments are not limited thereto, and other transistors and/or other circuit configurations may be used.”)
Regarding claim 18, Hwang/Hirose teaches the SRAM integrated circuit of claim 17, wherein the first NMOS and PMOS transistors are connected to form a first inverter, (Hwang, [0040]: “Similar to the SRAM circuit 200 shown in FIG. 2, the PU1 310 a and PD1 320 a are connected to make up one inverter,”) and wherein the second NMOS and PMOS transistors are connected to form a second inverter. (Hwang. [0040]: “and the PU2 310 b and the PD2 320 b are connected to make up another inverter.”)
Regarding claim 19, Hwang/Hirose teaches the SRAM integrated circuit of claim 18, wherein the first and second inverters are cross-coupled via frontside and backside cross-connects. (Hwang, [0006]: “a first shared contact and a second shared contact; a first cross-couple contact connecting the fourth shared gate and the first shared contact; and a second cross-couple contact connecting the third shared gate and the second shared contact.”)
Regarding claim 20, Hwang/Hirose teaches the SRAM integrated circuit of claim 18, wherein the third and fourth NMOS transistors are pass gate transistors. (Hwang, [0024]: “For example, a MOSFET described herein may take a different type or form of a transistor as long as the inventive concept can be applied thereto.”)
Regarding claim 21, Hwang teaches a static random access memory (SRAM) integrated circuit, (Hwang, FIG. 1-6C; “a static random access memory (SRAM)”) comprising: an upper layer and a lower layer separated by a dielectric layer; (Hwang, [0007]: “The method includes: providing a first metal gate as a first layer; providing a second metal gate as a second layer, the second layer being disposed above the first layer; performing a gate cutting through the first metal gate and the second metal gate; removing a portion of the second metal gate to form a first recess; filling the first recess with a first dielectric material; and providing a cross-couple contact on the second metal gate and a portion of the first dielectric material.”) first, second and third PMOS transistors formed in the upper layer; (Hwang provides for more than two PMOS transistors included in the plurality of transistors: [0037]: “Moreover, the PD1 220 a, the PD2 220 b, the PG1 230 a and the PG2 230 b may be n-type metal-oxide semiconductor (NMOS) transistors, and the PU1 210 a and the PU2 210 b may be a p-type metal-oxide semiconductor (PMOS) transistors. However, the one or more embodiments are not limited thereto, and other transistors and/or other circuit configurations may be used.”); a voltage supply rail, (Hwang, “voltage source”) a write word line, (Hwang, [0034]: “During the writing operation, for example, if an instruction to write a “1” in the memory cell is to be executed, the word line WL may be set high to turn on the PG1 130 a and the PG2 130 b”) a read bit line and a read word line formed in the upper layer; (Hwang, [0034]: “a value (i.e., “0” or “1”) in the memory cell may be read through a bit line BL”; [0034]: “During the reading operation, a word line WL may be set to high (i.e., logic state “1”) so as to activate access to the memory cell by the PG1 130 a and the PG2 130 b.”); first, second, third, fourth and a fifth NMOS transistors formed in the lower layer, wherein the plurality of PMOS transistors are vertically stacked over the plurality of NMOS transistors; (Hwang provides for more than two NMOS transistors included in the plurality of transistors: [0037]: “Moreover, the PD1 220 a, the PD2 220 b, the PG1 230 a and the PG2 230 b may be n-type metal-oxide semiconductor (NMOS) transistors, and the PU1 210 a and the PU2 210 b may be a p-type metal-oxide semiconductor (PMOS) transistors. However, the one or more embodiments are not limited thereto, and other transistors and/or other circuit configurations may be used.”) (Hwang, [0008]: “a static random access memory (SRAM) cell that includes two n-type metal oxide semiconductor (NMOS) transistors and two p-type metal oxide semiconductor (PMOS) transistors; an upper layer including the two PMOS transistors; a lower layer including the two NMOS transistors; a first shared contact and a second shared contact;”) a ground rail, (FIG. 3); wherein the first NMOS and PMOS transistors are connected to form a first inverter, (Hwang, [0040]: “Similar to the SRAM circuit 200 shown in FIG. 2, the PU1 310 a and PD1 320 a are connected to make up one inverter,”) and wherein the second NMOS and PMOS transistors are connected to form a second inverter. (Hwang. [0040]: “and the PU2 310 b and the PD2 320 b are connected to make up another inverter.”).
Hwang does not appear to explicitly teach a write bit line and a complementary write bit line formed in the lower layer; and a write word line contact extending from the upper layer into the lower layer to establish contact with a gate of the fifth NMOS transistor in the lower layer.
Hirose teaches a write bit line and a complementary write bit line formed in the lower layer; (Hirose, [0024]: “a fifth transistor having one node connected to a first write-bit line, another node connected to the first node, and a gate connected to a write-word line; a sixth transistor having one node connected to a second write-bit line constituting a complementary bit line pair with the first write-bit line, another node connected to the second node, and a gate connected to the write-word line;”) and a write word line contact extending from the upper layer into the lower layer to establish contact with a gate of the fifth NMOS transistor in the lower layer, (Hirose, for example, [0095]; “The line 71 is connected to the local interconnect 41i through a contact 91a, and connected to the local interconnect 41l through a contact 91b. The line 72 is connected to the local interconnect 41f through a contact 91c. The line 73 is connected to the local interconnect 41a through a contact 91d. The line 74 is connected to the local interconnect 41h through a contact 91e. The line 75 is connected to the gate line 31 through a contact (gate-contact) 61a, and connected to the line 81 through a contact 91f. The line 76 is connected to the gate line 34 through a contact 61d, and connected to the line 81 through a contact 91g. The line 77 is connected to the gate line 35 through a contact 61e, and connected to the line 82 through a contact 91h. That is, the line 81 is connected to the gate line 31 through the contact 91f, the line 75, and the contact 61c, and connected to the gate line 34 through the contact 91g, the line 76, and the contact 61d. The line 82 is connected to the gate line 35 through the contact 91h, the line 77, and the contact 61e.”)
Hwang and Hirose are both directed to semiconductor storage devices including a P-type FET and an N-type FET which are stacked forming a series of layers. It would have been obvious to one of ordinary skill in the art to combine the teachings of Hwang with the contacts of Hirose in order to teach the limitations set forth in the claim. One of ordinary skill in the art would have the motivation to combine the teachings in order to improve functionality of the semiconductor memory device.
Regarding claim 22, Hwang/Hirose teaches the SRAM integrated circuit of claim 21, wherein the first and second inverters are cross-coupled via frontside and backside cross-connects. (Hwang, [0006]: “a first shared contact and a second shared contact; a first cross-couple contact connecting the fourth shared gate and the first shared contact; and a second cross-couple contact connecting the third shared gate and the second shared contact.”)
Regarding claim 23, Hwang/Hirose teaches the SRAM integrated circuit of claim 21, further comprising a frontside interconnect electrically connected to the voltage supply rail, the write word line, the read bit line and the read word line. (Hirose, [0051]: “Two local interconnects 386 in contact with the P-type semiconductor layers 331p are formed so as to sandwich the gate configuration 391 in the X direction. Further, an N-type semiconductor layer 341n is formed to each end portion of two nanowires 358 far from the semiconductor substrate 101. Two local interconnects 388 in contact with the N-type semiconductor layers 341n are formed so as to sandwich the gate configuration 391 in the X direction. Between the local interconnects 386 and the local interconnects 388, insulating films 332 are formed. On the local interconnect 388, insulating films 389 are formed. For example, the P-type semiconductor layer 331p is a p-type SiGe layer, and the N-type semiconductor layer 341n is an n-type Si layer. For example, the insulating films 332 may be made of silicon oxide, silicon nitride, and the like.”)
Regarding claim 24, Hwang/Hirose teaches the SRAM integrated circuit of claim 21, further comprising a backside interconnect electrically connected to the ground rail, the write bit line and the complementary write bit line. (Hirose, [0051]: “Two local interconnects 386 in contact with the P-type semiconductor layers 331p are formed so as to sandwich the gate configuration 391 in the X direction. Further, an N-type semiconductor layer 341n is formed to each end portion of two nanowires 358 far from the semiconductor substrate 101. Two local interconnects 388 in contact with the N-type semiconductor layers 341n are formed so as to sandwich the gate configuration 391 in the X direction. Between the local interconnects 386 and the local interconnects 388, insulating films 332 are formed. On the local interconnect 388, insulating films 389 are formed. For example, the P-type semiconductor layer 331p is a p-type SiGe layer, and the N-type semiconductor layer 341n is an n-type Si layer. For example, the insulating films 332 may be made of silicon oxide, silicon nitride, and the like.”)
Allowable Subject Matter
All indefiniteness issues must be resolved and further search and consideration must be completed before indication of allowability can be made.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights