Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the preliminary amendment filed on 12/02/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 12, 24, 26, and 31 are objected to because of the following informalities:
Regarding claim 12, in line 9, “a first leg that coupled between the first voltage supply input and the input node” appears that it should read as “a first leg that is coupled between the first voltage supply input and the input node”.
Regarding claim 24, in line 1, “The low-dropout regulator it of claim 23” appears that it should read as “The low-dropout regulator of claim 23”.
Regarding claim 26, in line 2, “current limiter circuitry coupled a gate of the pass transistor” appears that it should read as “current limiter circuitry coupled to a gate of the pass transistor”.
Regarding claim 31, in line 1, “The power management integrated circuit it of claim 30” appears that it should read as “The power management integrated circuit of claim 30”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 31 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention. Regarding claim 31, the recitation “the pass transistor is configured to dissipate a majority of power in the low-dropout regulator” lacks proper antecedent basis. Claim 31 depends from claim 30, which ultimately depends from claim 27 directed to “a power management integrated circuit” comprising “a voltage regulation circuit”; neither claim 27 nor any intervening claim recites a “low-dropout regulator.” Accordingly, the metes and bounds of the claim cannot be ascertained. For purposes of examination, “the low-dropout regulator” is interpreted as “the power management integrated circuit.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12, 18, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Motz (US Patent Application Publication US 2010/0013448 A1) in view of LoCascio (US Patent 4,779,037).
Regarding claim 12, Motz discloses (see Fig. 2 and Fig. 4) a voltage regulation circuit (LDO voltage regulator 200) comprising: an error amplifier (operational transconductance amplifier (OTA) 122) configured to provide an error signal (a control voltage on OTA output path 134) based on a comparison of a reference voltage (provided by bandgap reference 116) and a voltage at a voltage divider (a resistor divide network including top resistor 118 and bottom resistor 120) coupled to an output node (VOUT 210) of the voltage regulation circuit (see [0040] of Motz “OTA 122 receives the reference voltage and the feedback voltage and provides a control voltage”); a pass transistor (regulation transistor 204) configured to selectively pass current from an input node (series transistor path 218) to the output node (VOUT 210) based on the error signal (see [0045] of Motz “drives and controls regulation transistor 110 to regulate output voltage”); and a first leg (the conduction path coupling power supply voltage VDD at 208 to series transistor path 218 through cascode transistor 202) coupled between the first voltage supply input (VDD 208) and the input node (series transistor path 218), wherein the first leg includes a transistor (cascode transistor 202) that is coupled in a cascode arrangement with the pass transistor (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Motz does not disclose switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node, the switching circuitry comprising the first leg and a second leg coupled between the second voltage supply input and the input node.
However, LoCascio teaches (see Fig. 2) switching circuitry (the supply-selection circuitry comprising series pass transistors Q1 and Q2) configured to selectively couple one of a first voltage supply input (V BAT) and a second voltage supply input (VCC) to the input node (the common node feeding the load through the conducting transistor), the switching circuitry comprising the first leg (the conduction path through transistor Q2 from V BAT) and a second leg (the conduction path through transistor Q1 from VCC) coupled between the second voltage supply input (VCC) and the input node (see Abstract of LoCascio “A first one of the transistors conducts when a first input voltage is greater than a second input voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz to include switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node, the switching circuitry comprising the first leg and a second leg coupled between the second voltage supply input and the input node, as taught by LoCascio, because it can help maintain a substantially constant low dropout output voltage before, during, and after a switch between two redundant supply inputs (e.g., upon a decrease or failure of the first voltage supply input).
Regarding claim 18, Motz does not disclose wherein the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage.
However, LoCascio teaches (see Fig. 2) wherein the first voltage supply input (V BAT) is configured to receive a first voltage (the battery voltage V BAT), the second voltage supply input (VCC) is configured to receive a second voltage (the voltage VCC across storage capacitor C1), and the first voltage is greater than the second voltage (see col. 3, lines 1-3 of LoCascio “V BAT will charge storage capacitor C1 through diode D10 until VCC equals V BAT minus the voltage drop”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz such that the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage, as taught by LoCascio, because it can help provide a higher-voltage primary supply together with a lower-voltage redundant supply that is charged therefrom and maintains the output during a decrease or failure of the primary supply.
Regarding claim 20, Motz discloses (see Fig. 2 and Fig. 4) a low-dropout regulator (LDO voltage regulator 200) comprising: an output node (VOUT 210); a voltage divider (a resistor divide network including top resistor 118 and bottom resistor 120) coupled to the output node; an error amplifier (operational transconductance amplifier (OTA) 122) configured to generate an error signal (a control voltage on OTA output path 134) based on a comparison of a reference voltage (provided by bandgap reference 116) and a voltage at the voltage divider (a feedback voltage on feedback input path 128) (see [0040] of Motz “OTA 122 receives the reference voltage and the feedback voltage and provides a control voltage”); a pass transistor (regulation transistor 204) configured to receive the error signal from the error amplifier and to selectively pass current from an input node (series transistor path 218) to the output node (VOUT 210) based on the error signal (see [0045] of Motz “drives and controls regulation transistor 110 to regulate output voltage”); and a first leg (the conduction path coupling power supply voltage VDD at 208 to series transistor path 218 through cascode transistor 202) coupled between a first voltage supply input (VDD 208) and the input node (series transistor path 218), wherein the first leg includes a cascode transistor (cascode transistor 202) that is coupled in a cascode arrangement with the pass transistor (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Motz does not disclose switching circuitry comprising the first leg and a second leg coupled between a second voltage supply input and the input node, wherein the second leg is coupled in parallel with the first leg.
However, LoCascio teaches (see Fig. 2) switching circuitry (the supply-selection circuitry comprising series pass transistors Q1 and Q2) comprising the first leg (the conduction path through transistor Q2 from V BAT) and a second leg (the conduction path through transistor Q1 from VCC) coupled between a second voltage supply input (VCC) and the input node, wherein the second leg is coupled in parallel with the first leg (see Abstract of LoCascio “A first one of the transistors conducts when a first input voltage is greater than a second input voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low-dropout regulator of Motz to include a second leg coupled between a second voltage supply input and the input node and coupled in parallel with the first leg, as taught by LoCascio, because it can help maintain a substantially constant output voltage before, during, and after a switch between two redundant supply inputs.
Regarding claim 25, Motz does not disclose wherein the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage.
However, LoCascio teaches (see Fig. 2) wherein the first voltage supply input (V BAT) is configured to receive a first voltage (the battery voltage V BAT), the second voltage supply input (VCC) is configured to receive a second voltage (the voltage VCC across storage capacitor C1), and the first voltage is greater than the second voltage (see col. 3, lines 1-3 of LoCascio “V BAT will charge storage capacitor C1 through diode D10 until VCC equals V BAT minus the voltage drop”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low-dropout regulator of Motz such that the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage, as taught by LoCascio, because it can help provide a higher-voltage primary supply together with a lower-voltage redundant supply that maintains the output during a decrease or failure of the primary supply.
Claims 13, 15, and 21–24 are rejected under 35 U.S.C. 103 as being unpatentable over Motz in view of LoCascio, and further in view of Ivanov et al. (US Patent Application Publication US 2019/0107857 A1, hereinafter “Ivanov”).
Regarding claim 13, Motz discloses (see Fig. 4) a cascode driver (the cascode voltage driver comprising switching circuit 224 and cascode compensation circuit 226) configured to control an amount of current passing through the transistor of the first leg (cascode transistor 202) (see [0060] of Motz “The offset voltage is added to the output voltage VOUT at 210 to provide the gate drive voltage for cascode transistor 202”).
Motz does not disclose a charge pump having an input coupled to the output node, wherein the charge pump is configured to generate a charge pump voltage.
However, Ivanov teaches (see Fig. 1 and Fig. 2) a charge pump (current mode charge pump 110) having an input coupled to the output node (the input of charge pump 110 receiving input voltage AVDD, coupled to the output node VOUT 210 of Motz in the combination), wherein the charge pump is configured to generate a charge pump voltage (output voltage Vout at output voltage node 112, twice the input voltage AVDD) (see [0021] of Ivanov “The charge pump 110 is able to achieve an output voltage Vout that is twice the input voltage AVDD”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz such that the cascode driver is configured to receive the charge pump voltage generated by the charge pump of Ivanov and to control the amount of current passing through the transistor of the first leg, the charge pump having an input coupled to the output node, as taught by Ivanov, because it can help provide a boosted gate-drive voltage to the high-voltage transistor of the first leg above its source and above the supply rail so as to keep the transistor of the first leg fully turned on and thereby maintain conduction and low-dropout output regulation as the supply voltage approaches the output voltage.
Regarding claim 15, Motz discloses (see Fig. 4) wherein the transistor of the first leg (cascode transistor 202) is a first nMOS power transistor having a first voltage rating (a high voltage rating, cascode transistor 202 being a high voltage NMOS transistor) and the pass transistor (regulation transistor 204) is a second nMOS power transistor having a second voltage rating that is less than the first voltage rating (a low voltage rating, regulation transistor 204 being a low voltage NMOS transistor) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Regarding claim 21, Motz discloses (see Fig. 4) a cascode driver (the cascode voltage driver comprising switching circuit 224 and cascode compensation circuit 226) configured to control an amount of current passing through the cascode transistor (cascode transistor 202) (see [0060] of Motz “The offset voltage is added to the output voltage VOUT at 210 to provide the gate drive voltage for cascode transistor 202”).
Motz does not disclose a charge pump having an input coupled to the output node, wherein the charge pump is configured to generate a charge pump voltage.
However, Ivanov teaches (see Fig. 1 and Fig. 2) a charge pump (current mode charge pump 110) having an input coupled to the output node (the input of charge pump 110 receiving input voltage AVDD, coupled to the output node VOUT 210 of Motz in the combination), wherein the charge pump is configured to generate a charge pump voltage (output voltage Vout at output voltage node 112, twice the input voltage AVDD) (see [0021] of Ivanov “The charge pump 110 is able to achieve an output voltage Vout that is twice the input voltage AVDD”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low-dropout regulator of Motz such that the cascode driver is configured to receive the charge pump voltage generated by the charge pump of Ivanov and to control the amount of current passing through the cascode transistor, the charge pump having an input coupled to the output node, as taught by Ivanov, because it can help provide a boosted gate-drive voltage to the high-voltage cascode transistor above its source and above the supply rail so as to keep the cascode transistor fully turned on and thereby maintain conduction and low-dropout output regulation as the supply voltage approaches the output voltage.
Regarding claim 22, Motz discloses (see Fig. 4) wherein the cascode transistor (cascode transistor 202) is a first nMOS power transistor having a first voltage rating (a high voltage rating, cascode transistor 202 being a high voltage NMOS transistor) and the pass transistor (regulation transistor 204) is a second nMOS power transistor having a second voltage rating that is less than the first voltage rating (a low voltage rating, regulation transistor 204 being a low voltage NMOS transistor) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Regarding claim 23, Motz does not explicitly disclose wherein, when the output node is shorted to ground and the first leg is active, the cascode transistor is configured to dissipate a first amount of power and the pass transistor is configured to dissipate a second amount of power that is less than the first amount of power.
However, Motz teaches (see Fig. 4) that the cascode transistor (cascode transistor 202) is a high voltage NMOS transistor coupled in series with the low voltage pass transistor (regulation transistor 204) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the cascode transistor of Motz to be configured to dissipate a first amount of power and the pass transistor be configured to dissipate a second amount of power that is less than the first amount of power, when the output node is shorted to ground and the first leg is active, as taught by Motz, because the high voltage cascode transistor coupled in series with the low voltage pass transistor necessarily sustains and dissipates the majority of the voltage between the first voltage supply input and the shorted output node while the low voltage pass transistor drops the remainder (see Examiner’s Note below).
Examiner’s Note: regarding the power-dissipation limitations of claims 16, 17, 23, 24, 30, and 31: The recited power-dissipation distribution is an inherent and necessary property of the series cascode structure disclosed by Motz, and is not a separately patentable feature. The cascode transistor (cascode transistor 202) and the pass transistor (regulation transistor 204) are connected in series along a single conduction path between a voltage supply input and the output node, and therefore carry the same current. The power dissipated in each transistor equals the product of the voltage across it and the current through it. Because the same current flows through both series-connected transistors, the transistor that sustains the larger voltage necessarily dissipates the larger amount of power. When the output node is shorted to zero volts and the first leg is active, substantially the entire voltage between the selected voltage supply input and the shorted output node is dropped across the series combination of the cascode transistor and the pass transistor. The cascode transistor is a high-voltage NMOS device having a higher voltage rating than the low-voltage pass transistor, as established by claims 15, 22, and 29, and is the device positioned to block and sustain the majority of that voltage, while the low-voltage source-follower pass transistor sustains only the smaller remainder. Consequently, the cascode transistor necessarily dissipates the first (greater) amount of power and the pass transistor necessarily dissipates the second (lesser) amount of power, as recited in claims 16, 23, and 30. This power-dissipation relationship is the very purpose for which a high-voltage cascode device is placed in series with a low-voltage pass transistor, and it is present in the structure of Motz without further modification. When the output node is shorted to zero volts and the second leg is active, the second leg is the parallel path that does not include the cascode transistor, so that the pass transistor is the sole series element between the second voltage supply input and the shorted output node. The pass transistor therefore necessarily sustains, and dissipates a majority of the power associated with, the entire voltage difference between the second voltage supply input and the shorted output node, as recited in claims 17, 24, and 31. This too is a necessary consequence of the prior-art structure and requires no further modification. Accordingly, the power-dissipation limitations of claims 16, 17, 23, 24, 30, and 31 are met by the prior-art structure by inherency.
Regarding claim 24, Motz does not explicitly disclose wherein, when the output node is shorted to zero volts and the second leg is active, the pass transistor is configured to dissipate a majority of power in the low-dropout regulator.
However, Motz teaches (see Fig. 4) a pass transistor (regulation transistor 204) coupled between the input node (series transistor path 218) and the output node (VOUT 210) (see [0052] of Motz “Regulation transistor 204 is a low voltage NMOS transistor in a source follower configuration”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pass transistor of Motz to be configured to dissipate a majority of power in the low-dropout regulator when the output node is shorted to zero volts and the second leg is active, as taught by Motz, because the second leg does not include the cascode transistor and the pass transistor is then the sole series element that sustains and dissipates the voltage difference between the second voltage supply input and the shorted output node (see Examiner’s Note following claim 23).
Claims 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Motz in view of LoCascio and Ivanov, and further in view of Turkson et al. (US Patent Application Publication US 2020/0076430 A1, hereinafter “Turkson”).
Regarding claim 14, Motz does not disclose a first switch included in the first leg; a second switch included in the second leg; and one or more switch drivers coupled to the first switch and the second switch and configured to control the first switch and the second switch.
However, Turkson teaches (see Fig. 2) a first switch (first switch circuit 210, connected between first input voltage source node 214 and the output voltage node 206) included in the first leg; a second switch (second switch circuit 220, connected between second input voltage source node 224 and the output voltage node 206) included in the second leg; and one or more switch drivers (first driver circuit 230 and second driver circuit 234) coupled to the first switch and the second switch and configured to control the first switch and the second switch (see [0024] of Turkson “The first switch circuit 210 and the second switch circuit 220 is driven by a respective driver circuit shown as a first driver circuit 230 driving the first switch circuit and a second driver circuit 234 driving the second switch circuit”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz to include a first switch in the first leg, a second switch in the second leg, and one or more switch drivers configured to control the first switch and the second switch, as taught by Turkson, because it can help select and connect a desired one of the two voltage supply inputs to the input node with a controlled switchover, thereby mitigating output voltage drooping and inrush current during the transition from one voltage supply input to the other.
Regarding claim 16, Motz does not explicitly disclose wherein, when the output node is at zero volts and the first voltage supply input is selected, the transistor of the first leg is configured to dissipate a majority of power in the voltage regulation circuit.
However, Motz teaches (see Fig. 4) that the transistor of the first leg (cascode transistor 202) is a high voltage NMOS transistor coupled in series with the low voltage pass transistor (regulation transistor 204) between the first voltage supply input (VDD 208) and the output node (VOUT 210) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the transistor of the first leg of Motz to be configured to dissipate a majority of power in the voltage regulation circuit when the output node is at zero volts and the first voltage supply input is selected, as taught by Motz, because a high voltage transistor coupled in series with a low voltage transistor necessarily sustains and dissipates the majority of the voltage difference between the first voltage supply input and the shorted output node (see Examiner’s Note following claim 23).
Regarding claim 17, Motz does not explicitly disclose wherein, when the output node is at zero volts and the second voltage supply input is selected, the pass transistor is configured to dissipate a majority of power in the voltage regulation circuit.
However, Motz teaches (see Fig. 4) a pass transistor (regulation transistor 204) coupled between the input node (series transistor path 218) and the output node (VOUT 210) (see [0052] of Motz “Regulation transistor 204 is a low voltage NMOS transistor in a source follower configuration”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pass transistor of Motz to be configured to dissipate a majority of power in the voltage regulation circuit when the output node is at zero volts and the second voltage supply input is selected, as taught by Motz, because the second leg does not include the cascode transistor and the pass transistor is then the sole series element that sustains and dissipates the voltage difference between the second voltage supply input and the shorted output node (see Examiner’s Note following claim 23).
Claims 19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Motz in view of LoCascio, and further in view of Hamon et al. (US Patent Application Publication US 2003/0147193 A1, hereinafter “Hamon”).
Regarding claim 19, Motz does not disclose current limiter circuitry coupled to a gate of the pass transistor and configured to limit current through the pass transistor.
However, Hamon teaches (see Fig. 2 and Fig. 3) current limiter circuitry (current-limiting device 8) coupled to a gate of the pass transistor (the gate of P-channel MOS power transistor T1) and configured to limit current through the pass transistor (see [0027] of Hamon “Device 8 is further connected to the gate of transistor T1”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz to include current limiter circuitry coupled to a gate of the pass transistor and configured to limit current through the pass transistor, as taught by Hamon, because it can help protect the regulator and the load against excessive current by setting a maximum current that the regulator provides.
Regarding claim 26, Motz does not disclose current limiter circuitry coupled to a gate of the pass transistor and configured to limit current through the pass transistor.
However, Hamon teaches (see Fig. 2 and Fig. 3) current limiter circuitry (current-limiting device 8) coupled to a gate of the pass transistor (the gate of P-channel MOS power transistor T1) and configured to limit current through the pass transistor (see [0027] of Hamon “Device 8 is further connected to the gate of transistor T1”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low-dropout regulator of Motz to include current limiter circuitry coupled to a gate of the pass transistor and configured to limit current through the pass transistor, as taught by Hamon, because it can help protect the regulator and the load against excessive current by setting a maximum current that the regulator provides.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Motz in view of LoCascio, and further in view of Adest et al. (US Patent Application Publication US 2008/0136367 A1, hereinafter “Adest”).
Regarding claim 27, Motz discloses (see Fig. 2 and Fig. 4) a voltage regulation circuit (LDO voltage regulator 200) configured to generate a regulated output voltage at an output node (VOUT 210), the voltage regulation circuit comprising: a voltage divider (a resistor divide network including top resistor 118 and bottom resistor 120) coupled to the output node; an error amplifier (operational transconductance amplifier (OTA) 122) configured to generate an error signal (a control voltage on OTA output path 134) based on a comparison of a reference voltage (provided by bandgap reference 116) and a voltage at the voltage divider (see [0040] of Motz “OTA 122 receives the reference voltage and the feedback voltage and provides a control voltage”); a pass transistor (regulation transistor 204) configured to receive the error signal from the error amplifier and to selectively pass current from an input node (series transistor path 218) to the output node (VOUT 210) based on the error signal (see [0045] of Motz “drives and controls regulation transistor 110 to regulate output voltage”); and switching circuitry comprising a first leg (the conduction path through cascode transistor 202 to series transistor path 218) wherein the first leg includes a cascode transistor (cascode transistor 202) coupled in a cascode arrangement with the pass transistor (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Motz does not disclose a second leg coupled between a second voltage supply and the input node, wherein the second leg is coupled in parallel with the first leg.
However, LoCascio teaches (see Fig. 2) switching circuitry (the supply-selection circuitry comprising series pass transistors Q1 and Q2) comprising a first leg (the conduction path through transistor Q2 from a first supply) coupled between a first voltage supply and the input node and a second leg (the conduction path through transistor Q1 from a second supply) coupled between a second voltage supply and the input node, wherein the second leg is coupled in parallel with the first leg (see Abstract of LoCascio “A first one of the transistors conducts when a first input voltage is greater than a second input voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz to include a second leg coupled between a second voltage supply and the input node, wherein the second leg is coupled in parallel with the first leg, as taught by LoCascio, because it can help maintain a substantially constant output voltage before, during, and after a switch between two redundant supply inputs.
Motz does not disclose a battery; and a direct-current (DC)-DC converter coupled to the battery, wherein the first leg is coupled between the battery and the input node and the second leg is coupled between the DC-DC converter and the input node.
However, Adest teaches (see Fig. 1 and Fig. 5) a power management integrated circuit comprising a battery (battery cells 102) and a direct-current (DC)-DC converter (DC to DC conversion unit 506) coupled to the battery (see [0046] of Adest “DC to DC voltage conversion unit 506 is included to provide the host device with the desired voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulation circuit of Motz to include a battery and a direct-current (DC)-DC converter coupled to the battery, the first leg being coupled between the battery and the input node and the second leg being coupled between the DC-DC converter and the input node, as taught by Adest, because it can help provide the host device with a desired, regulated voltage from the battery with high digital power conversion efficiency over a wide range of loads.
Claims 28–31 are rejected under 35 U.S.C. 103 as being unpatentable over Motz in view of LoCascio and Adest, and further in view of Ivanov.
Regarding claim 28, Motz discloses (see Fig. 4) a cascode driver (the cascode voltage driver comprising switching circuit 224 and cascode compensation circuit 226) configured to control an amount of current passing through the cascode transistor (cascode transistor 202) (see [0060] of Motz “The offset voltage is added to the output voltage VOUT at 210 to provide the gate drive voltage for cascode transistor 202”).
Motz does not disclose a charge pump having an input coupled to the output node, wherein the charge pump is configured to generate a charge pump voltage.
However, Ivanov teaches (see Fig. 1 and Fig. 2) a charge pump (current mode charge pump 110) having an input coupled to the output node (the input of charge pump 110 receiving input voltage AVDD, coupled to the output node VOUT 210 of Motz in the combination), wherein the charge pump is configured to generate a charge pump voltage (output voltage Vout at output voltage node 112, twice the input voltage AVDD) (see [0021] of Ivanov “The charge pump 110 is able to achieve an output voltage Vout that is twice the input voltage AVDD”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power management integrated circuit of Motz such that the cascode driver is configured to receive the charge pump voltage generated by the charge pump of Ivanov and to control the amount of current passing through the cascode transistor, the charge pump having an input coupled to the output node, as taught by Ivanov, because it can help provide a boosted gate-drive voltage to the high-voltage cascode transistor above its source and above the supply rail so as to keep the cascode transistor fully turned on and thereby maintain conduction and low-dropout output regulation as the supply voltage approaches the output voltage.
Regarding claim 29, Motz discloses (see Fig. 4) wherein the cascode transistor (cascode transistor 202) is a first nMOS power transistor having a first voltage rating (a high voltage rating, cascode transistor 202 being a high voltage NMOS transistor) and the pass transistor (regulation transistor 204) is a second nMOS power transistor having a second voltage rating that is less than the first voltage rating (a low voltage rating, regulation transistor 204 being a low voltage NMOS transistor) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Regarding claim 30, Motz does not explicitly disclose wherein, when the output node is shorted to ground and the first leg is active, the cascode transistor is configured to dissipate a first amount of power and the pass transistor is configured to dissipate a second amount of power that is less than the first amount of power.
However, Motz teaches (see Fig. 4) that the cascode transistor (cascode transistor 202) is a high voltage NMOS transistor coupled in series with the low voltage pass transistor (regulation transistor 204) (see [0052] of Motz “Cascode transistor 202 is a high voltage NMOS transistor coupled in series with regulation transistor 204”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the cascode transistor of Motz to be configured to dissipate a first amount of power and the pass transistor be configured to dissipate a second amount of power that is less than the first amount of power, when the output node is shorted to ground and the first leg is active, as taught by Motz, because the high voltage cascode transistor coupled in series with the low voltage pass transistor necessarily sustains and dissipates the majority of the voltage between the battery and the shorted output node while the low voltage pass transistor drops the remainder (see Examiner’s Note following claim 23).
Regarding claim 31, as best understood, Motz does not explicitly disclose wherein, when the output node is shorted to zero volts and the second leg is active, the pass transistor is configured to dissipate a majority of power in the power management integrated circuit (“the low-dropout regulator,” as interpreted under the 35 U.S.C. 112(b) rejection above).
However, Motz teaches (see Fig. 4) a pass transistor (regulation transistor 204) coupled between the input node (series transistor path 218) and the output node (VOUT 210) (see [0052] of Motz “Regulation transistor 204 is a low voltage NMOS transistor in a source follower configuration”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the pass transistor of Motz to be configured to dissipate a majority of power in the power management integrated circuit when the output node is shorted to zero volts and the second leg is active, as taught by Motz, because the second leg does not include the cascode transistor and the pass transistor is then the sole series element that sustains and dissipates the voltage difference between the DC-DC converter and the shorted output node (see Examiner’s Note following claim 23).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0036432 A1 discloses a voltage regulator using two different pass transistors with two different turn-on threshold voltages and two different maximum drain-to-source voltage ratings. US 2018/0284826 A1 discloses a voltage regulator using two different pass transistors with two different input voltage levels. US 7,148,587 B2 discloses a voltage regulator with a plurality of input terminals connected to a plurality of DC power supplies.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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