Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on July 29th, 2026. Claims 18-37 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/11/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12189560. Although the claims at issue are not identical, they are not patentably distinct from each other as shown by the following table (provided for illustrative purposes) that compares claim 1 of the instant application with claim 1 of the issued Patent.
Co-pending Application (#18/965046)
18.) A method of training a physical interface between a first device and a second device, the method comprising:
performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes;
performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group, wherein the first candidate group of lanes and the second candidate group of lanes are included in a high bandwidth memory (HBM) interface of the physical interface, wherein the HBM interface connects the first device and the second device;
determining a lane group based on a result of the first training and a result of the second training; and
setting the second device so that the determined lane group is used for the physical interface,
wherein the second device includes a plurality of memory dies that are stacked;
Claim 1, Issued Patent No. 12189560
1. ) A method of training a physical interface between a first device and a second device, the method comprising:
determining a timing of a signal transmission in a first candidate group, from a plurality of lanes between the first device and the second device, by performing a first training of the physical interface, the first training including temporarily setting the first candidate group and communicating a signal between the first device and the second device using the first candidate group of lanes from among the plurality of lanes;
determining a timing of a signal transmission in a second candidate group, from the plurality of lanes between the first device and the second device, by performing a second training of the physical interface, the second training including temporarily setting the second candidate group and communicating a signal between the first device and the second device using the second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group;
determining a lane group based on a comparison of the timings determined during the first training and the second training; and
setting the second device SO that the determined lane group is used for the physical interface,
wherein the physical interface includes a high bandwidth memory (HBM) interface and the second device includes a plurality of memory dies that are stacked.
Although the conflicting claims are not identical, the instant application claim scope is a genus to the issued Patent’s species scope, the instant application incorporating material already present in the issued Patent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-25, and 27-37 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI et al. (USPGPUB No. 2021/0182223 A1, hereinafter referred to as CHOI) in view of Shokrollahi et al. (USPGPUB No. 2019/0179791 A1, hereinafter referred to as Shokrollahi).
Referring to claim 18, CHOI discloses a method of training a physical interface between a first device and a second device {“select an internal [physical interface] DBI scheme corresponding to the data parallelizing system shown in FIG. 5”, and also see Fig. 1, [0067]}, the method comprising:
performing a first training of the physical interface {“the DBI controller (110 of FIG. 1) may [performing a first training] determine the internal DBI scheme in accordance [with the physical interface]”, see Figs. 1 and 2, [0054], 1st sentence}, by communicating with the second device {“receive [by communicating] provision of (e.g. may receive) the data parallelizing information 212 from the memory device 200”, see Fig. 2, [0051], 1st sentence} by using a first candidate group of lanes from among a plurality of lanes {“is a first case (case 1) [for a first candidate group]”, see Fig. 2, [0053]};
performing a second training of the physical interface {“additionally [repeatable/second training], in some example embodiments, the DBI controller (e.g. DBI controller 110 of FIG. 1) may determine the internal DBI scheme in accordance with the internal data parallelizing system of the memory device (200 of FIG. 1), for example, using hardware such as a fuse and/or an antifuse”, see Fig. 2, [0054], last sentence}, by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes {“is a first case (case 1) [for a first candidate group]”, see Fig. 2, [0053]}, the second candidate group being different from the first candidate group {“Specifically, the table 122 may include different internal DBI schemes for each data mapping case”, Figure 2 illustrating N different cases for candidate lane groups, [0704], last sentence.};
wherein the first candidate group of lanes and the second candidate group of lanes {“table 122 may include different internal DBI schemes for each data mapping case [for the respective group of lanes]”, see Fig. 2, [0053], 2nd sentence} are included in a high bandwidth memory (HBM) interface of the physical interface {“a high-bandwidth memory (HBM) which provides a multi-channel interface type of wide input and output is used”, see Figs. 1 and 2, [0004]}, wherein the HBM interface connects the first device and the second device {“memory device 200 may be a high-bandwidth memory (HBM) that provides a multi-channel interface type of wide input and output”, see Figs. 1 and 2, [0028].}
CHOI does not appear to disclose determining a lane group based on a result of the first training and a result of the second training;
and setting the second device so that the determined lane group is used for the physical interface, wherein the physical interface includes a high bandwidth memory (HBM) interface, and the second device includes a plurality of memory dies that are stacked.
However, Shokrollahi discloses determining a lane group based on a result of the first training {“[a lane group] total of eight wires used for each CNRZ-5 instance”, see Fig. 3 , [0086], last sentence} and a result of the second training {“Each CNRZ-5 transmitter 340 accepts five data bits from Data Funneling 310”, see Fig. 3, [0089], 2nd sentence};
and setting the second device {“the HBM channel 101 being processed by HBM to [second device] EHBM translator 102”, see Fig. 1, [0049], 2nd sentence} so that the determined lane group is used for the physical interface {“collection of such EHBM [candidate lane group] physical transport wires for all channels constitutes the complete [physical interface] PHY Interface”, see Fig. 1, [0049], last two sentences}, wherein the physical interface includes a high bandwidth memory (HBM) interface {“EHBM PHY 104”, see Fig. 3, [0089], 1stsentence}, and the second device includes a plurality of memory dies {“HBM DRAM memory dies using TSVs”, [0047]} that are stacked {“EHBM interconnection between a host or controller device and at least one HBM DRAM stack”, [0109]}.
CHOI and Shokrollahi are analogous because they are from the same field of endeavor, high performance architecture.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI and Shokrollahi before him or her, to modify CHOI’s “select an internal [physical interface] DBI scheme corresponding” (see Fig. 1 and 5, [0067]) incorporating Shokrollahi’s “expands the representative channel 100 of FIG. 1 to” (see Fig. 3, [0070]).
The suggestion/motivation for doing so would have been to implement a number of connections to a controller device such as a GPU uses significant I/O pad “beachfront” on the controller die, creating a scalability barrier to future system requirements for two or more HBM connections to provide greater memory bandwidth or larger total memory size (Shokrollahi [0018], last sentence).
Therefore, it would have been obvious to combine Shokrollahi with CHOI to obtain the invention as specified in the instant claim(s).
As per claim 19, the rejection of claim 18 is incorporated and CHOI discloses further comprising:
selecting the second candidate group {“a second case case 2”, see Figs. 1 and 2, [0053], last sentence} among the plurality of lanes {“determine the [second candidate group] external DBI bits (EDBI0 to EDBI6 of FIG. 9) constituting/corresponding to the external DBI information 6”, see Fig. 9, [0077], 1st sentence} based on the result of the first training {“[first training] sub-data D0 and the sub-data D1 which are output through the output ports DQ0, DQ1, DQ2, DQ3, and DQ4 of the host 100”, see Figs. 1-6 [0075]}.
As per claim 20, the rejection of claim 19 is incorporated and Shokrollahi discloses wherein the performing of the first training comprises:
detecting a plurality of first valid window margins {“values are only valid when the link is in [window margin] frame”, see Figs. 6, 7, and 8 [0140], last two sentences}, each valid window margin {“specific EHBM transfer widths and numbers of transfer cycles”, see Figs. 6, 7, and 8 [0108], 2nd sentence} in the plurality of first valid window margins corresponding to a lane {“the EHBM [lanes] data paths are narrower”, see Fig. 6, 7, and 8 [0102]} from among the lanes in the first candidate group {“half-duplex individually clocked CNRZ-5 channels”, see Fig. 9 [0101], 1st sentence}, and wherein the performing of the first training comprises:
identifying a first lane corresponding {“the data paths in the HBM to EHBM direction”, see Fig. 6 [0094], 1st sentence} to a minimum first valid window margin {“utilizes its own [minimum valid] clock to capture received data at each unit interval.”, see Fig. 5 [0091], 1st sentence} of the plurality of first valid window margins {“values are only valid when the link is in [window margin] frame”, see Figs. 6, 7, and 8 [0140], last two sentences};
and selecting lanes from among the plurality of lanes excluding {“HBM itself has two mutually exclusive modes for the 16 DM_CB bits”, see Figs. 6, 7, and 8, [0254]} the first lane as the second candidate group {“EHBM interface has twenty-five sub-channels, numbered SC(24:0). Table II of FIG. 11 shows”, [0174]}.
As per claim 21, the rejection of claim 20 is incorporated and Shokrollahi discloses wherein the selecting of the second candidate group comprises:
detecting a plurality of second valid window margins {“values are only valid when the link is in [window margin] frame”, see Figs. 6, 7, and 8 [0140], last two sentences}, each valid window margin {“specific EHBM transfer widths and numbers of transfer cycles”, see Figs. 6, 7, and 8 [0108], 2nd sentence} in the plurality of second valid window margins corresponding to a lane {“the EHBM [lanes] data paths are narrower”, see Fig. 6, 7, and 8 [0102]} from among the lanes in the second candidate group {“half-duplex individually clocked CNRZ-5 channels”, see Fig. 9 [0101], 1st sentence}, and wherein the performing of the second training comprises:
identifying a second lane corresponding {“the data paths in the EHBM to HBM direction”, see Fig. 7 [0096], 1st sentence} to a minimum second valid window margin {“utilizes its own [minimum valid] clock to capture received data at each unit interval.”, see Fig. 5 [0091], 1st sentence} of the plurality of second valid window margins {“values are only valid when the link is in [window margin] frame”, see Figs. 6, 7, and 8 [0140], last two sentences};
identifying a higher valid window margin {“the EHBM physical transport layer is narrower but operate at significantly higher speed”, see Fig. 3, [0071]} among the minimum first valid window margin and the minimum second valid window margin {“A separate clock pair is used for or each CNRZ-5 channel to minimize the effects of skew”, [0086], last sentence};
and selecting a candidate group {“five control/status bits from Command Formatting 320 as selected by multiplexers 650 and 660 (shown in FIG. 6)”, [0089]} corresponding to the identified higher valid window margin {“[valid window] turn-around time to switch the direction of the duplex transmission between transfers”, [0105]} among the first candidate group {“one CNRZ-5 instance 1050 is dedicated to operation in the memory to host direction”, see Fig. 10, [0104]} and the second candidate group {“EHBM interface has twenty-five sub-channels, numbered SC(24:0). Table II of FIG. 11 shows”, [0174]}, as the determined lane group {“four CNRZ-5 instances capable of bidirectional operation 1060 are assigned to either host to memory or memory to host operation”, [0104]}.
As per claim 22, the rejection of claim 19 is incorporated and Shokrollahi discloses wherein the selecting of the second candidate group comprises:
identifying deactivation of at least one function of the physical interface {“buffering via [as well as deactivating] latches may be combined with a data funneling function”, see Fig. 4, [0093], 1st sentence};
and selecting the second candidate group {“five control/status bits from Command Formatting 320 as selected by multiplexers 650 and 660 (shown in FIG. 6)”, [0089]} such that the second candidate group includes at least one lane that is unused as a result of the at least one function {“128 HBM data bits with 16 bits of write data mask” ([0077]), “Data Bus Inversion offers” ([0186]), “Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])} being in a deactivated state {“consecutively enabling [or disabling] different latches on successive receive unit intervals”, see Fig. 6, [0093]}.
As per claim 23, the rejection of claim 22 is incorporated and Shokrollahi discloses wherein the at least one function comprises:
at least one of a data masking function {“128 HBM data bits with 16 bits of write data mask”, [0077]}, a data bus inversion function {“Data Bus Inversion offers” ([0186])}, and an error correction function {“Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])}.
As per claim 24, the rejection of claim 18 is incorporated and Shokrollahi discloses further comprising:
performing a third training by communicating with the second device by using a third candidate group of lanes {“enabling or disabling one or more [lanes] portions of the MUX circuit”, see Figs. 70 and 71, [0634]} from among the plurality of lanes {“control the control channels [lanes] of the multiplexer circuit 8736”, see Figs. 70 and 71 [0683]}, the third candidate group being different from the first candidate group and different from the second candidate group {“each HBM half-transfer (i.e. the 64 bits of data transferred per HBM clock transition) is buffered separately”, [0091], last sentence}, wherein the determined lane group is determined based on a result of the first training {“[a lane group] total of eight wires used for each CNRZ-5 instance”, see Fig. 3, [0086], last sentence}, a result of the second training {“Each CNRZ-5 transmitter 340 accepts five data bits from Data Funneling 310”, see Fig. 3, [0089], 2nd sentence}, and a result of the third training {“Each CNRZ-5 transmitter 340 accepts five data bits from Data Funneling 310”, see Fig. 3, [0089], 2nd sentence}.
Claim 25 is rejected 35 U.S.C. 103 as being unpatentable over CHOI in view of Shokrollahi and further in view of Xia et al. (USPGPUB No. 2015/0055947 A1, hereinafter referred to as Xia).
As per claim 25, the rejection of claim 18 is incorporated however neither CHOI or Shokrollahi appears to disclose any limitation recited in this dependent claim.
However, Xia discloses verifying lanes between the first device and the second device from among the plurality of lanes {“confirms the identified wavelength channel”, see Fig. 7, [0044]}, wherein the first candidate group and the second candidate group include lanes {“optionally communicate with the newly deployed optical port 220 to confirm the identified wavelength channel”, see Fig. 7, [0044]}, from among the plurality of lanes {lane group “the group of unallocated wavelength channels”, see Fig. 7, [0046]}, that are determined to be valid lanes as a result of the verifying {“write the confirmation or information regarding the suggested changes”, see Fig. 7, last 5 lines of [0044]}.
CHOI/Shokrollahi and Xia are analogous because they are from the same field of endeavor, lane management.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI/Shokrollahi and Xia before him or her, to modify CHOI/Shokrollahi’s system incorporating Xia’s “port discovery circuit 110” (see Fig. 6).
The suggestion/motivation for doing so would have been to implement a realizing a converged WDM optical network is optical port discovery due to the limited capability of logic processing on optical signals for aggregating traffic of multiple series (Xia [0003], last sentence).
Therefore, it would have been obvious to combine Xia with CHOI/Shokrollahi to obtain the invention as specified in the instant claim(s).
Claims 27, 29, 30, 31, 32, 34, 35, 36, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of Shokrollahi and further in view of Kale (US Pat No. 12182704 B2).
Referring to claim 27, CHOI discloses a first device configured to communicate with a second device based on a physical interface {first device “host SOC 100” to “receive [by communicating] provision of (e.g. may receive) the data parallelizing information 212 from the memory device 200”, see Figs. 1 and 2, [0051], 1st sentence}, the first device comprising:
wherein the first candidate group of lanes and the second candidate group of lanes {“table 122 may include different internal DBI schemes for each data mapping case [for the respective group of lanes]”, see Fig. 2, [0053], 2nd sentence} are included in a high bandwidth memory (HBM) interface of the physical interface {“a high-bandwidth memory (HBM) which provides a multi-channel interface type of wide input and output is used”, see Figs. 1 and 2, [0004]}, wherein the HBM interface connects the first device and the second device {“memory device 200 may be a high-bandwidth memory (HBM) that provides a multi-channel interface type of wide input and output”, see Figs. 1 and 2, [0028].}
CHOI does not appear to explicitly disclose routing circuit configured to select some of a plurality of lanes based on a control signal, for the physical interface;
and generate the control signal for training the physical interface by using each of different candidate groups of lanes from among the plurality of lanes, and determine a lane group to be used for the physical interface based on a result of the training;
However, Shokrollahi discloses routing circuit {“Each CNRZ-5 transmitter 340 accepts five data bits from Data Funneling 310”, see Fig. 3, [0089], 2nd sentence} configured to select some of a plurality of lanes based {“[a lane group] total of eight wires used for each CNRZ-5 instance”, see Fig. 3, [0086], last sentence} on a control signal, for the physical interface {“EHBM translator 102” handling a plurality of control signals, see Fig. 1, [0049], 2nd sentence};
and generate the control signal for training the physical interface {“the HBM channel 101 being processed by HBM to [second device] EHBM translator 102” and their respective control signals, see Fig. 1, [0049], 2nd sentence} by using each of different candidate groups of lanes from among the plurality of lanes {“collection of such EHBM [candidate lane group] physical transport wires for all channels constitutes the complete [physical interface] PHY Interface”, see Fig. 1, [0049], last two sentences}, and determine a lane group to be used for the physical interface {“[a lane group] total of eight wires used for each CNRZ-5 instance”, see Fig. 3, [0086], last sentence} based on a result of the training {“Each CNRZ-5 transmitter 340 accepts five data bits from Data Funneling 310”, see Fig. 3, [0089], 2nd sentence}; and the second device includes a plurality of memory dies that are stacked {“EHBM interconnection between a host or controller device and at least one HBM DRAM stack”, [0109]};
CHOI and Shokrollahi are analogous because they are from the same field of endeavor, high performance computing architecture.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI and Shokrollahi before him or her, to modify CHOI’s “select an internal [physical interface] DBI scheme corresponding” (see Fig. 1 and 5, [0067]) and Shokrollahi’s “expands the representative channel 100 of FIG. 1 to” (see Fig. 3, [0070]).
The suggestion/motivation for doing so would have been to implement a number of connections to a controller device such as a GPU uses significant I/O pad “beachfront” on the controller die, creating a scalability barrier to future system requirements for two or more HBM connections to provide greater memory bandwidth or larger total memory size (Shokrollahi [0018], last sentence).
Therefore, it would have been obvious to combine Shokrollahi with CHOI to obtain the invention as specified in the instant claim(s).
Neither CHOI or Shokrollahi appears to explicitly disclose wherein the second device includes a plurality of memory dies that are stacked.
Kale discloses wherein the second device includes a plurality of memory dies that are stacked {“integrated circuit device 101 is configured with a high bandwidth connection 119 between the random access memory 105 and the deep learning accelerator (DLA) 103”, see Fig. 1, Col 7, lines 46-50 ;“integrated circuit device (101) has multiple stacked integrated circuit dies that are connected using through-silicon vias”, see Fig. 9, Col 24, lines 53-54}.
CHOI/Shokrollahi and Kale are analogous because they are from the same field of endeavor, lane management.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI/Shokrollahi and Kale before him or her, to modify CHOI/Shokrollahi’s system incorporating Kale’s “deep learning accelerator” (see Fig. 1, Col 7, lines 21-23).
The suggestion/motivation for doing so would have been to implement the granularity of the deep learning accelerator (DLA) can be configured to increase the ratio between the amount of computations performed by the deep learning accelerator (DLA) and the size of the vector/matrix operands such that the data access traffic between the deep learning accelerator (DLA) and the random access memory can be reduced, which can reduce the requirement on the communication bandwidth between the deep learning accelerator (DLA) and the random access memory which in turn can reduce or eliminate the bottleneck in data/memory access (Kale Col 4, lines 34-43).
Therefore, it would have been obvious to combine Kale with CHOI/Shokrollahi to obtain the invention as specified in the instant claim(s).
As per claim 29, the rejection of claim 27 is incorporated and Shokrollahi discloses, wherein the processing circuitry is further configured to identify deactivation of at least one function of the physical interface {“buffering via [as well as deactivating] latches may be combined with a data funneling function”, see Fig. 4, [0093], 1st sentence}, and generate the control signal for training the physical interface based on a candidate group of lanes {“five control/status bits from Command Formatting 320 as selected by multiplexers 650 and 660 (shown in FIG. 6)”, [0089]}, from among the plurality of lanes, that includes at least one lane that is unused as a result of the at least one function {“128 HBM data bits with 16 bits of write data mask” ([0077]), “Data Bus Inversion offers” ([0186]), “Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])} being in a deactivated state {“consecutively enabling [or disabling] different latches on successive receive unit intervals”, see Fig. 6, [0093]}.
As per claim 30, the rejection of claim 29 is incorporated and Shokrollahi discloses wherein the at least one deactivated function includes at least one of a data masking function {“128 HBM data bits with 16 bits of write data mask”, [0077]}, a data bus inversion function {“Data Bus Inversion offers” ([0186])}, and an error correction function {“Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])}.
As per claim 31, the rejection of claim 27 is incorporated and Shokrollahi discloses wherein the processing circuitry is further configured to verify lanes between the first device and the second device from among the plurality of lanes {“confirms the identified wavelength channel”, see Fig. 7, [0044]}, and perform a training for the physical interface {“enabling or disabling one or more [lanes] portions of the MUX circuit”, see Figs. 70 and 71, [0634]} among a candidate group that includes lanes {“optionally communicate with the newly deployed optical port 220 to confirm the identified wavelength channel”, see Fig. 7, [0044]}, from among the plurality of lanes {lane group “the group of unallocated wavelength channels”, see Fig. 7, [0046]}, that are determined to be valid lanes as a result of the verifying {“write the confirmation or information regarding the suggested changes”, see Fig. 7, last 5 lines of [0044]}.
Referring to claim 32 is a system claims reciting claim functionality corresponding to the device claim of claim 27, respectively, inter alia, Choi discloses wherein the first candidate group of lanes and the second candidate group of lanes {“table 122 may include different internal DBI schemes for each data mapping case [for the respective group of lanes]”, see Fig. 2, [0053], 2nd sentence} are included in a high bandwidth memory (HBM) interface of the physical interface {“a high-bandwidth memory (HBM) which provides a multi-channel interface type of wide input and output is used”, see Figs. 1 and 2, [0004]}, wherein the HBM interface connects the first device and the second device {“memory device 200 may be a high-bandwidth memory (HBM) that provides a multi-channel interface type of wide input and output”, see Figs. 1 and 2, [0028].};
Kale discloses wherein the physical interface includes a high bandwidth memory (HBM) interface {“integrated circuit device 101 is configured with a high bandwidth connection 119 between the random access memory 105 and the deep learning accelerator (DLA) 103”, see Fig. 1, Col 7, lines 46-50}, wherein the second device includes a plurality of memory dies that are stacked {“integrated circuit device (101) has multiple stacked integrated circuit dies that are connected using through-silicon vias”, see Fig. 9, Col 24, lines 53-54};
wherein the plurality of interconnections include at least one through silicon {“connected using through-silicon vias (TSV) for increased data bandwidth”, see Figs. 1 and 2, Col 9, lines 21-25} via penetrating at least one of the plurality of memory dies {“ Through-silicon vias (TSVs) from the substrate integrated circuit die to the other integrated circuit dies stacked on it (and/or underneath it) can be used to provide the connections”, see Fig. 6, Col 22, line 65 through Col 23, line 3}.
CHOI/Shokrollahi and Kale are analogous because they are from the same field of endeavor, lane management.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI/Shokrollahi and Kale before him or her, to modify CHOI/Shokrollahi’s system incorporating Kale’s “deep learning accelerator” (see Fig. 1, Col 7, lines 21-23).
The suggestion/motivation for doing so would have been to implement the granularity of the deep learning accelerator (DLA) can be configured to increase the ratio between the amount of computations performed by the deep learning accelerator (DLA) and the size of the vector/matrix operands such that the data access traffic between the deep learning accelerator (DLA) and the random access memory can be reduced, which can reduce the requirement on the communication bandwidth between the deep learning accelerator (DLA) and the random access memory which in turn can reduce or eliminate the bottleneck in data/memory access (Kale Col 4, lines 34-43).
Therefore, it would have been obvious to combine Kale with CHOI/Shokrollahi to obtain the invention as specified in the instant claim(s).
As per claim 34, the rejection of claim 32 is incorporated and Shokrollahi discloses wherein the first device and the second device are further configured to train the physical interface using a candidate group {“buffering via [as well as deactivating] latches may be combined with a data funneling function”, see Fig. 4, [0093], 1st sentence}, from among the plurality of different candidate groups, that includes at least one interconnection {“five control/status bits from Command Formatting 320 as selected by multiplexers 650 and 660 (shown in FIG. 6)”, [0089]}, from among the plurality of interconnections, that is unused as a result of at least one function of the physical interface {“128 HBM data bits with 16 bits of write data mask” ([0077]), “Data Bus Inversion offers” ([0186]), “Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])} being set in a deactivated state {“consecutively enabling [or disabling] different latches on successive receive unit intervals”, see Fig. 6, [0093]}.
As per claim 35, the rejection of claim 34 is incorporated and Shokrollahi discloses wherein the at least one function comprises:
at least one of a data masking function {“128 HBM data bits with 16 bits of write data mask”, [0077]}, a data bus inversion function {“Data Bus Inversion offers” ([0186])}, and an error correction function {“Forward Error Correction (FEC) is a highly appropriate alternative” ([0207])}.
As per claim 36, the rejection of claim 32 is incorporated and Shokrollahi discloses wherein the plurality of interconnections are included, respectively, in a plurality of lanes {“HBM DBI (Data Bus Inversion) line code is at the HBM interface”, [0199], 1st sentence}, and the first device is further configured to verify the plurality of lanes {“confirms the identified wavelength channel”, see Fig. 7, [0044]}, and wherein the first device and the second device are further configured to perform a training for the physical interface {“enabling or disabling one or more [lanes] portions of the MUX circuit”, see Figs. 70 and 71, [0634]} based on a candidate group {“optionally communicate with the newly deployed optical port 220 to confirm the identified wavelength channel”, see Fig. 7, [0044]}, from among the plurality of different candidate groups {lane group “the group of unallocated wavelength channels”, see Fig. 7, [0046]}, that include interconnections which are included in valid lanes from among the plurality of lanes {“write the confirmation or information regarding the suggested changes”, see Fig. 7, last 5 lines of [0044]}.
As per claim 37, the rejection of claim 32 is incorporated and Kale discloses wherein the first device includes a base die {“formed on an [based] integrated circuit die stacked above one or more integrated circuit dies of the random access memory”, see Fig. 6, Col 22, lines 42-43}, and wherein the plurality of memory dies are stacked on the base die {“integrated circuit device (101) has multiple stacked integrated circuit dies that are connected using through-silicon vias”, see Fig. 9, Col 24, lines 53-54}.
Claims 28 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI in view of Shokrollahi and further in view of Kale and further in view of Xia.
As per claim 28, the rejection of claim 27 is incorporated however neither one from the group consisting of CHOI, Shokrollahi, and Kale appears to explicitly disclose any limitation in this dependent claim.
However, Xia discloses wherein the processing circuitry is further configured to detect a plurality of minimum valid window margins corresponding {“during a transmission test”, see Fig. 7, [0044]}, respectively, to a plurality of trainings {“read the [first and second training results] overhead messages containing the explicit wavelength channel information”, see Fig. 7, [0046]}, and determine, as the determined the lane group, a candidate group of lanes {“may suggest that the wavelength selection circuit 130 increase the slot width”, see Fig. 7, [0044]}, from among the plurality of lanes, corresponding to a highest value among the plurality of minimum valid window margins {these transmission tests can occur simultaneously “discovers a predefined set of one or more attributes of port33a”, see Fig. 7, [0042]}.
CHOI/Shokrollahi/Kale and Xia are analogous because they are from the same field of endeavor, lane management.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CHOI/Shokrollahi and Xia before him or her, to modify CHOI/Shokrollahi’s system incorporating Xia’s “port discovery circuit 110” (see Fig. 6).
The suggestion/motivation for doing so would have been to implement a realizing a converged WDM optical network is optical port discovery due to the limited capability of logic processing on optical signals for aggregating traffic of multiple series (Xia [0003], last sentence).
Therefore, it would have been obvious to combine Xia with CHOI/Shokrollahi to obtain the invention as specified in the instant claim(s).
As per claim 33, the rejection of claim 32 is incorporated however neither one from the group consisting of CHOI, Shokrollahi, and Kale appears to explicitly disclose any limitation in this dependent claim.
However, Xia discloses wherein the processing circuitry is further configured to detect a plurality of minimum valid window margins corresponding {“during a transmission test”, see Fig. 7, [0044]}, respectively, to a plurality of trainings {“read the [first and second training results] overhead messages containing the explicit wavelength channel information”, see Fig. 7, [0046]}, and determine, as the determined the lane group, a candidate group of lanes {“may suggest that the wavelength selection circuit 130 increase the slot width”, see Fig. 7, [0044]}, from among the plurality of lanes, corresponding to a highest value among the plurality of minimum valid window margins {these transmission tests can occur simultaneously “discovers a predefined set of one or more attributes of port33a”, see Fig. 7, [0042]}.
The 103 motivation for this dependent claim relied upon as recited in claim 28 above.
Allowable Subject Matter
Claim 26 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed on 07/29/2026 have been considered however deemed moot in view of the new ground of rejection(s).
Additionally, Applicant alleges that the Shokro reference is silent to the claim 18 limitations “determining a lane group” (Remarks page 10, item 5)
The Examiner will elaborate the claim interpretation to claim 18, and then draw parallels to the references, in particular Shokro. Claim 18 recites comprising preamble, treated as an open-ended claim, meaning other undisclosed structure/functionality/steps as long as facilitate the current disclosed structure/functionality/steps. Claim 18 recites a step “determining a candidate group lanes”, however the term “lanes” and “determining” does not further specific hardware/software/logic to performing such steps, let alone how many wires, pins, or fanout corresponding to each lane, as in 1:1, 1:N, M:N, where M many to N many such elements to “lane”.
Turning to the specification PGPUB, the exact phrasing “first candidate group of lanes” recited either in the SUMMARY ([0005]) or the claims themselves. A further Figure 4A, one could surmise “output the data signal DQ to the first pins P11 through P18, or may receive the data signal DQ from the first pins P11 through P18” ([0053], 3rd sentence) stand in for the contested limitations until the Applicant/Counsel incorporates a clearer definition to the independent claim(s) 18, 27, and 32.
In lieu of the claim interpretation above, Shokro discloses training “command formatting 320” with the use of “Data Funneling 310” as the plurality of “CNRZ-5” in both directions as expanded in Figure 6 HBM lane groups “DQ 610” and “selector signals 633” which direct Multiplexors 650 and 660 to select appropriate subsets of inputs for transmission in consecutive EHBM unit intervals (see Fig. 6, [0095]) transmitting from HBM to EHBM; conversely for the other direction, “FIG. 7 details the data paths in the EHBM to HBM direction” ([0096], 1st sentence) that shares an expanded version in Figure 8. In other words, even though Shokro does not recite the terms “lane” explicitly, the above rebuttal concerning Figures 6 and 7 illustrates and demonstrates equivalent functionality recited in the claims 18, 27, and 32.
For these reasons the current ground of rejection(s) is respectfully maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative the current state of the art regarding claim 18’s “training a physical interface”, “a plurality of memory dies”, or “HBM interface”: US 12541411 B2, US 12003610 B1, US 20230168984 A1, US 20220050698 A1, and US 20100306429 A1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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