The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (18/965,086) filed on December 2, 2024.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on December 2, 2024 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on December 2, 2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103(a) as being disclosed by Byun et al. (US PGPUB 2020/0174668 hereinafter referred to as Byun), in view of Muchherla et al. (US PGPUB 2022/0199184 hereinafter referred to as Muchherla), in view of Saxena et al. (US PGPUB 2020/0097403 hereinafter referred to as Saxena) and further in view of UM et al. (US PGPUB 2016/0328155 hereinafter referred to as UM).
As per independent claim 1, Byun discloses an operating method of a processor of a storage device, the operating method comprising: performing a first garbage collection operation on first sub-blocks of a non-volatile memory, each of the first sub-blocks having a first block size; and performing a second garbage collection operation on second sub-blocks of the non-volatile memory, each of the second sub-blocks having a second block size [(Paragraphs 0092-0098; FIGs. 1 and 6) wherein the first garbage collection performer GCO1 may copy valid pages of the victim blocks selected by the first victim block selector VBS1 to empty pages of a free block. Next, the first garbage collection performer GCO1 may erase the victim blocks and set the erased victim blocks to free blocks. For example, cold block 12 and cold block 20 that are selected as victim blocks by the first victim block selector VBS1 through the first method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 12 and cold block 20 selected as victim blocks to empty pages of a free block. Next, after all pages included in cold block 12 and cold block 20 have been erased, cold block 12 and cold block 20 may be set to free blocks. Next, cold block 31 that is selected as a victim block by the first victim block selector VBS1 through the second method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 31 selected as a victim block to empty pages of a free block. Next, after all pages included in cold block 31 have been erased, cold block 31 may be set to a free block; Next, the second garbage collection component 136C to be operated when the garbage collection urgent level is determined to be a high level will be described. In the case where the garbage collection level determination component 136A determines the garbage collection urgent level to be a high level, the second garbage collection component 136C may be selected and operated in order to generate a free block in a short time. The second garbage collection component 136C may include a second victim block selector VBS2, and a second garbage collection performer GCO2 to correspond to the claimed limitation].
Byun does not appear to explicitly disclose the second block size being different from the first block size.
However, Muchherla discloses the second block size being different from the first block size [(Paragraphs 0042-0043; FIGs. 1 and 2B) where FIG. 2B is a further example schematic diagram of data selection from multiple sub-blocks of a wordline for performing scanning of the wordline, in accordance with some embodiments. In another embodiment, a memory portion 130B of the memory device 130 contains multiple pages corresponding to multiple sub-blocks. In one embodiment, the memory portion 130B is a more-detailed version of the memory portion 130A discussed with reference to FIG. 2A. The memory portion 130A is illustrated as having four sub-blocks (numbered 0, 1, 2, and 3 for purposes of explanation), but fewer or more sub-blocks can define multiple wordlines (WL0 . . . WL3) in different embodiments. The memory portion 130A can be understood to illustrate one implementation in which each sub-block is 16 kilobytes (KB) in size, which includes four groups of memory cells, each being 4 KB in size, but different sizes of each sub-block and each group of sub-blocks are envisioned to correspond to the claimed limitation].
Byun and Muchherla are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun and Muchherla before him or her, to modify the device of Byun to include the sub-blocks of Muchherla because it will enhance memory performance.
The motivation for doing so would be [“reducing the overhead costs associated with multiple reads of individual sub-blocks, and corresponding error check of each sub-block. Because at least a chunk of data is sampled form each sub-block, all of the multiple sub-blocks are effectively scanned as a set, e.g., pseudo-page” (Paragraph 0019 by Muchherla)].
Byun does not appear to explicitly disclose wherein the performing of the first garbage collection operation comprises: selecting, as a first victim sub-block, a sub-block with a lowest valid page count from among the first sub-blocks; and wherein the performing of the second garbage collection operation comprises: selecting a second victim sub-block from among the second sub-blocks.
However, Saxena discloses wherein the performing of the first garbage collection operation comprises: selecting, as a first victim sub-block, a sub-block with a lowest valid page count from among the first sub-blocks; and wherein the performing of the second garbage collection operation comprises: selecting a second victim sub-block from among the second sub-blocks [(Paragraphs 0026 and 0044; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. Correlatively, a block is a logically closed block if the last write offset of the block is set to the block size, which indicates that no more additional writes are possible. Furthermore, it is noted that garbage collection operations are typically performed on closed blocks to correspond to the claimed limitation].
Byun and Saxena are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun and Saxena before him or her, to modify the device of Byun to include the memory stacks of Saxena because it will enhance memory buffering.
The motivation for doing so would be [“provide improved sustained write performance and block endurance for NVMs due to reduced garbage collection operations” (Paragraph 0056 by Saxena)].
Byun further teaches copying a valid page of the first victim sub-block to a first target sub-block from among the first sub-blocks; and performing a first erase operation on the first victim sub-block; copying a valid page of the second victim sub-block to a second target sub-block from among the second sub-blocks; and performing a second erase operation on the second victim sub-block [(Paragraphs 0092-0094; FIGs. 1 and 6) wherein the first garbage collection performer GCO1 may copy valid pages of the victim blocks selected by the first victim block selector VBS1 to empty pages of a free block. Next, the first garbage collection performer GCO1 may erase the victim blocks and set the erased victim blocks to free blocks. For example, cold block 12 and cold block 20 that are selected as victim blocks by the first victim block selector VBS1 through the first method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 12 and cold block 20 selected as victim blocks to empty pages of a free block. Next, after all pages included in cold block 12 and cold block 20 have been erased, cold block 12 and cold block 20 may be set to free blocks. Next, cold block 31 that is selected as a victim block by the first victim block selector VBS1 through the second method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 31 selected as a victim block to empty pages of a free block. Next, after all pages included in cold block 31 have been erased, cold block 31 may be set to a free block to correspond to the claimed limitation].
Byun/ Saxena does not appear to explicitly disclose performing a first erase operation on the first victim sub-block; and performing a second erase operation on the second victim sub-block.
However, Um discloses performing a first erase operation on the first victim sub-block; and performing a second erase operation on the second victim sub-block [(Paragraphs 0006, 0059 and 0067-0069; FIGs. 1, 4 and 6) where the erase operation unit 1348 erases the victim blocks VICTIM1 and VICTIM2 upon completion of the update of the mapping table of the storage unit 1442, which is due to the copying of the data stored in the valid pages of the victim blocks VICTIM1 and VICTIM2 to the free block FREE1. Therefore, all the pages stored in the victim blocks VICTIM1 and VICTIM2 are converted into erased states and free states through the garbage collection operation to correspond to the claimed limitation].
Byun and Saxena are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun and Saxena before him or her, to modify the device of Byun to include the memory stacks of Saxena because it will enhance memory buffering.
The motivation for doing so would be [“memory system capable of supporting a garbage collection operation and an operating method thereof.” (Paragraph 0002 by UM)].
Therefore, it would have been obvious to combine Byun and Saxena to obtain the invention as specified in the instant claim.
Claim 2 is rejected under 35 U.S.C. 103(a) as being disclosed by Byun/ Muchherla/ Saxena/ Um, as applied to claim 1, and further in view of Puthenthermadam et al. (US PGPUB 2022/0180948 hereinafter referred to as Puthenthermadam).
As per dependent claim 2, Byun/ Muchherla/ Saxena/ Um discloses the operating method of claim 1.
Byun/ Muchherla/ Saxena/ Um does not appear to explicitly disclose wherein: the first sub-blocks respectively correspond to first memory stacks on a substrate, and the second sub-blocks respectively correspond to second memory stacks on the first memory stacks.
However, Puthenthermadam discloses wherein: the first sub-blocks respectively correspond to first memory stacks on a substrate, and the second sub-blocks respectively correspond to second memory stacks on the first memory stacks [(Paragraphs 0047 and 0114; FIGs. 1 and 7A) wherein when sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged vertically on top of another sub-block), erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. In addition, during the erase operation, the holes necessary for erasing one sub-block (e.g., gate-induced drain leakage (GIDL) based hole generation or holes supplied by a PWELL instead of GIDL based hole generation) can be blocked by the sub-block that is inhibited from erasing, when sub-blocks are arranged with contiguous (adjacent) word lines so that the sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged on top of another sub-block), such as what is described in FIG. 7B above, erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. For example, in FIG. 9A, a first sub-block SB0 associated with a lower tier of the stack (i.e., the first sub-block SB0 is a source side adjacent sub-block) is arranged below a second sub-block SB1 associated with an upper tier of the stack (i.e., the second sub-block SB1 is a drain side adjacent sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding with the first sub-block SB0 (selected one of the first and second blocks SB0, SB1) have a word line erase voltage VERA_WL_L1 (e.g., 0.5 volts) applied to them to encourage erasing of the memory cells connected to the word lines corresponding with the first sub-block SB0 to correspond to the claimed limitation].
Byun/ Muchherla/ Saxena/ Um and Puthenthermadam are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun/ Muchherla/ Saxena/ Um and Puthenthermadam before him or her, to modify the device of Byun/ Muchherla/ Saxena/ Um to include the memory stacks of Puthenthermadam because it will enhance memory buffering.
The motivation for doing so would be [“the erase speed of the selected sub-block (the one being erased) is improved” (Paragraph 0116 by Puthenthermadam)].
Therefore, it would have been obvious to combine Byun/ Muchherla/ Saxena/ Um and Puthenthermadam to obtain the invention as specified in the instant claim.
Claim 3 is rejected under 35 U.S.C. 103(a) as being disclosed by Byun/ Muchherla/ Saxena/ Um, as applied to claim 1, and further in view of Higgins et al. (US 9,652,381 hereinafter referred to as Higgins).
As per dependent claim 3, Byun/ Muchherla/ Saxena/ Um discloses the operating method of claim 1.
Byun/ Muchherla/ Saxena/ Um does not appear to explicitly disclose wherein: the first garbage collection operation is performed independently from the second garbage collection operation, based on a block size of the first sub-blocks and the second sub-blocks.
However, Higgins discloses wherein: the first garbage collection operation is performed independently from the second garbage collection operation, based on a block size of the first sub-blocks and the second sub-blocks [(Column 2, lines 56-67, Column 3, lines 1-4, 56-59 and Column 12, lines 15-29) wherein Higgins teaches determining a first trigger parameter in accordance with one or more operating conditions of a first sub-block of an erase block in the storage medium and determining a second trigger parameter in accordance with one or more operating conditions of a second sub-block of the erase block in the storage medium. In accordance with a determination that the first trigger parameter meets a first vulnerability criterion, garbage collection of the first sub-block is enabled, and in accordance with a determination that the second trigger parameter meets a second vulnerability criterion, garbage collection of the second sub-block is enabled; where the first vulnerability criterion is distinct from the second vulnerability criterion; in some implementations, one or more sub-blocks in a block are of different size than other sub-blocks in the same block. For example, a particularly vulnerable page or word line can be its own sub-block, while other sub-blocks of the same block contain multiple pages or word lines and thus are multiple times as large as the sub-block that is particularly vulnerable. In another example of sub-blocks having different sizes and different vulnerability criterions, one sub-block can be a subset of another, larger sub-block, with the smaller sub-block having a distinct vulnerability criterion than the larger sub-block. In this way, the smaller sub-block can be configured to protect data in a particularly vulnerable portion of a block by assigning it a different vulnerability criterion (e.g., a smaller read count threshold) than the larger sub-block to correspond to the claimed limitation].
Byun/ Muchherla/ Saxena/ Um and Higgins are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun/ Muchherla/ Saxena/ Um and Higgins before him or her, to modify the device of Byun/ Muchherla/ Saxena/ Um to include the independent garbage collection operations of Higgins because it will enhance memory buffering.
The motivation for doing so would be [“Reducing write amplification, through improved garbage collection, improves the life and performance of a flash-based storage system” (Column 1, lines 52-55 by Higgins)].
Therefore, it would have been obvious to combine Byun/ Muchherla/ Saxena/ Um and Higgins to obtain the invention as specified in the instant claim.
Claims 4-6 are rejected under 35 U.S.C. 103(a) as being disclosed by Byun/ Muchherla/ Saxena/ Um, as applied to claim 1, and further in view of You et al. (US PGPUB 2020/0409836 hereinafter referred to as You).
As per dependent claim 4, Byun/ Muchherla/ Saxena/ Um discloses the operating method of claim 1.
Byun discloses wherein the copying of the valid page of the first victim sub-block comprises: copying the valid page of the first victim sub-block to the first target sub-block, based on a first garbage collection management table of the first sub-blocks; and wherein the copying of the valid page of the second victim sub-block comprises: copying the valid page of the second victim sub-block to the second target sub-block, based on a second garbage collection management table of the second sub-blocks [(Paragraphs 0092-0094; FIGs. 1 and 6) where the first garbage collection performer GCO1 may copy valid pages of the victim blocks selected by the first victim block selector VBS1 to empty pages of a free block. Next, the first garbage collection performer GCO1 may erase the victim blocks and set the erased victim blocks to free blocks. For example, cold block 12 and cold block 20 that are selected as victim blocks by the first victim block selector VBS1 through the first method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 12 and cold block 20 selected as victim blocks to empty pages of a free block. Next, after all pages included in cold block 12 and cold block 20 have been erased, cold block 12 and cold block 20 may be set to free blocks. Next, cold block 31 that is selected as a victim block by the first victim block selector VBS1 through the second method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 31 selected as a victim block to empty pages of a free block. Next, after all pages included in cold block 31 have been erased, cold block 31 may be set to a free block to correspond to the claimed limitation].
Byun/ Muchherla/ Saxena/ Um does not appear to explicitly disclose the second victim sub-block having a lowest valid page count from among the second sub-blocks.
However, You discloses the second victim sub-block having a lowest valid page count from among the second sub-blocks [(Paragraphs 0008, 0068 and 0208-0209; FIGs 2 and 16) where the write handler 210 may select at least one of the victim blocks so as to perform the garbage collection operation. Closed blocks may Include valid data and invalid data therein. The victim block may be determined according to an amount of the valid data or the invalid data, which is included in the closed blocks. For example, memory blocks of which the amount of valid data is a certain amount or less may be selected as victim blocks among the memory blocks. The garbage collection operation of FIG. 16 may be performed through steps S1 to S3. In the step S1, block 0 (BLK0) and block 1 (BLK1) are selected as victim blocks (Victim BLK0 and Victim BLK1). A method for selecting victim blocks may be performed based on various references. For example, memory blocks in which the amount of valid data is a certain level or less may be selected as victim blocks. Alternatively, victim blocks may be selected using a ratio of valid data to invalid data to correspond to the claimed limitation.
Byun/ Muchherla/ Saxena/ Um and Higgins are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun/ Muchherla/ Saxena/ Um and You before him or her, to modify the device of Byun/ Muchherla/ Saxena/ Um to include the valid page count of You because it will enhance memory buffering.
The motivation for doing so would be [“efficiently control the dummy memory cell(s)” (Paragraph 0127 by You)].
Therefore, it would have been obvious to combine Byun/ Muchherla/ Saxena/ Um and You to obtain the invention as specified in the instant claim.
As per dependent claim 5, Byun discloses wherein: the first garbage collection management table is configured to store a valid page count of each of the first sub-blocks, and the second garbage collection management table is configured to store a valid page count of each of the second sub-blocks [(Paragraphs 0092-0094; FIGs. 1 and 6) where first garbage collection performer GCO1 may copy valid pages of the victim blocks selected by the first victim block selector VBS1 to empty pages of a free block. Next, the first garbage collection performer GCO1 may erase the victim blocks and set the erased victim blocks to free blocks. For example, cold block 12 and cold block 20 that are selected as victim blocks by the first victim block selector VBS1 through the first method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 12 and cold block 20 selected as victim blocks to empty pages of a free block. Next, after all pages included in cold block 12 and cold block 20 have been erased, cold block 12 and cold block 20 may be set to free blocks. Next, cold block 31 that is selected as a victim block by the first victim block selector VBS1 through the second method will be described. The first garbage collection performer GCO1 may copy valid pages of cold block 31 selected as a victim block to empty pages of a free block. Next, after all pages included in cold block 31 have been erased, cold block 31 may be set to a free block to correspond to the claimed limitation].
As per dependent claim 6, UM discloses wherein the performing of the first garbage collection operation further comprises: updating the first garbage collection management table after copying the valid page of the first victim sub-block to the first target sub-block, and wherein the performing of the second garbage collection operation further comprises: updating the second garbage collection management table after copying the valid page of the second victim sub-block to the second target sub-block [(Paragraphs 0006, 0059 and 0067-0069; FIGs. 1, 4 and 6) where the erase operation unit 1348 erases the victim blocks VICTIM1 and VICTIM2 upon completion of the update of the mapping table of the storage unit 1442, which is due to the copying of the data stored in the valid pages of the victim blocks VICTIM1 and VICTIM2 to the free block FREE1. Therefore, all the pages stored in the victim blocks VICTIM1 and VICTIM2 are converted into erased states and free states through the garbage collection operation to correspond to the claimed limitation].
Claim 7 is rejected under 35 U.S.C. 103(a) as being disclosed by Byun/ Muchherla/ Saxena/ Um, as applied to claim 1, and further in view of You et al. (US PGPUB 2020/0409836 hereinafter referred to as You).
As per dependent claim 7, Byun/ Muchherla/ Saxena/ Um discloses the operating method of claim 1.
Byun/ Muchherla/ Saxena/ Um does not appear to explicitly disclose wherein: each of the first sub-blocks is coupled to a first word line group comprising a plurality of first word lines stacked in a vertical direction, each of the second sub-blocks is coupled to a second word line group comprising a plurality of second word lines stacked in the vertical direction, and a number of first word lines comprised by the plurality of first word lines is different from a number of second word lines comprised by the plurality of second word lines.
However, You discloses wherein: each of the first sub-blocks is coupled to a first word line group comprising a plurality of first word lines stacked in a vertical direction [(Paragraphs 0004, 0113 and 0154-0155; FIGs. 1, 4 and 8) wherein You teaches wherein in FIG. 4, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., a +X direction). Although FIG. 4 illustrates two cell strings arranged in a column direction (i.e., a +Y direction), the present disclosure is not limited thereto. That is, the two string arrangement shown in FIG. 4 is for clarity of illustration to correspond to the claimed limitation], each of the second sub-blocks is coupled to a second word line group comprising a plurality of second word lines stacked in the vertical direction [(Paragraphs 0004, 0113 and 0154-0155; FIGs. 1, 4 and 8) wherein You teaches wherein in FIG. 4, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., a +X direction). Although FIG. 4 illustrates two cell strings arranged in a column direction (i.e., a +Y direction), the present disclosure is not limited thereto. That is, the two string arrangement shown in FIG. 4 is for clarity of illustration to correspond to the claimed limitation], and a number of first word lines comprised by the plurality of first word lines is different from a number of second word lines comprised by the plurality of second word lines [(Paragraphs 0146, 0153 and 0161-0163; FIGs 3 and 7) where the main block may include zeroth to nth pages Page 0 to Page n. Each page may be configured with memory cells coupled to one word line. For example, memory cells coupled to a zeroth word line may constitute the zeroth page, and memory cells coupled to a first word line may constitute the first page to correspond to the claimed limitation].
Byun/ Muchherla/ Saxena/ Um and You are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun/ Muchherla/ Saxena/ Um and You before him or her, to modify the device of Byun/ Muchherla/ Saxena/ Um to include the memory stacks of You because it will enhance memory buffering.
The motivation for doing so would be [“ efficiently control the dummy memory cell(s)” (Paragraph 0127 by You)].
Therefore, it would have been obvious to combine Byun/ Muchherla/ Saxena/ Um and You to obtain the invention as specified in the instant claim.
Claim 8 is rejected under 35 U.S.C. 103(a) as being disclosed by Byun/ Muchherla/ Saxena/ Um, as applied to claim 1, in view of Lien et al. (US PGPUB 2023/0069260 hereinafter referred to as Lien).
As per dependent claim 8, Byun/ Muchherla/ Saxena/ Um discloses the storage device of claim 1.
Byun/ Muchherla/ Saxena/ Um does not appear to explicitly disclose controlling, in a first mode, the first erase operation on the non-volatile memory in sub-block units; and controlling, in a second mode, the second erase operation on the non-volatile memory in block units, wherein each of the block units comprise at least two sub-blocks.
Lien discloses wherein the processor is further configured to: control, in a first mode, a first erase operation on the non-volatile memory in sub-block units; and control, in a second mode, a second erase operation on the non-volatile memory in block units, wherein each of the block units comprises at least two sub-blocks [(Paragraphs 0142, 0204 and 0266; FIGs. 1, 4 and 6) wherein in an erase operation, typically the entire block is erased. Another option is a partial block erase in which one or more selected sub-blocks are erased. In an erase operation for a sub-block, an erase-verify test can be performed for the entire sub-block block or for one NSG at a time to correspond to the claimed limitation].
Byun/ Muchherla/ Saxena/ Um and Lien are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Byun/ Muchherla/ Saxena/ Um and Lien before him or her, to modify the device of You to include the different erasing modes of Lien because it will enhance memory allocation.
The motivation for doing so would be [“allows the user to erase a smaller unit of memory cells rather than erasing the entire block. Additionally, if a defective word line is detected, the corresponding individual sub-block can be marked as bad while the remaining sub-blocks can still be used. There is no need to abandon the entire block. A further advantage is that some types of data require a designated region which cannot be shared with other types of data. By allocating a sub-block instead of an entire block as the designated region, additional savings are achieved” (Paragraphs 0055-0056 by Lien)].
Therefore, it would have been obvious to combine Byun/ Muchherla/ Saxena/ Um and Lien to obtain the invention as specified in the instant claim.
Claim 10-12 are rejected under 35 U.S.C. 103(a) as being disclosed by You et al. (US PGPUB 2020/0409836 hereinafter referred to as You), in view of Muchherla, and further in view of Muchherla et al. (US PGPUB 2022/0199184 hereinafter referred to as Muchherla), and further in view of Puthenthermadam et al. (US PGPUB 2022/0180948 hereinafter referred to as Puthenthermadam).
As per independent claim 10, You discloses a storage device [(Paragraph 0046; FIG. 1) wherein You teaches storage device 50 that includes a memory device 100 and a memory controller 200 to correspond to the claimed limitation], comprising: a non-volatile memory comprising a plurality of memory stacks [(Paragraphs 0004, 0050-0051, 0083 and 0288; FIGs. 1 and 8 ) wherein You teaches where the memory device 2200 may be implemented with various nonvolatile memory devices such as an Electrically Erasable and Programmable ROM (EPROM), a NAND flash memory. the memory device 100 of the present disclosure may perform an erase operation in units of sub-blocks. When one memory block includes a plurality of sub-blocks, the memory device 100 may erase a specific sub-block in the memory block. That is, the memory device 100 may erase a portion of the memory block. In this specification, the memory block is defined as a main block. One main block may include a plurality of sub-blocks, and the size of the sub-block may be changed by the memory controller 200 to correspond to the claimed limitation] that are independently erasable [(Paragraphs 0004, 0050-0051, 0083 and 0288; FIGs. 1 and 8) wherein You teaches where the memory device 100 may erase a specific sub-block in the memory block. That is, the memory device 100 may erase a portion of the memory block. In this specification, the memory block is defined as a main block. One main block may include a plurality of sub-blocks, and the size of the sub-block may be changed by the memory controller 200 to correspond to the claimed limitation], each memory stack of the plurality of memory stacks extending in a vertical direction on a substrate [(Paragraphs 0111 and 0155; FIGs 1 and 3-5) where the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along +X, +Y, and +Z directions. A structure of each memory block will be described in more detail with reference to FIGS. 4 and 5 to correspond to the claimed limitation]; and a storage controller comprising a processor configured to control a garbage collection operation on the plurality of memory stacks [(Paragraphs 0004, 0050-0051 and 0060-0062; FIGs. 1 and 8) wherein You teaches where the memory controller 200 may further include a write handler 210. The write handler 210 may receive and process a write request input from the host 300. When the write request is input from the host 300, the write handler 210 may determine whether the number of currently free blocks in the memory device 100 is sufficient. When the number of currently free blocks is not sufficient, the write handler 210 may perform a garbage collection operation for securing more free blocks to correspond to the claimed limitation], wherein the plurality of memory stacks comprises: a plurality of first memory stacks arranged on the substrate [(Paragraphs 0111 and 0155; FIGs 1 and 3-5) where the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along +X, +Y, and +Z directions. A structure of each memory block will be described in more detail with reference to FIGS. 4 and 5 to correspond to the claimed limitation], each first memory stack of the plurality of first memory stacks being coupled to a first word line group and having a first size, the first word line group comprising a plurality of first word lines stacked in the vertical direction [(Paragraphs 0004, 0113 and 0154-0155; FIGs. 1, 4 and 8) wherein You teaches wherein in FIG. 4, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., a +X direction). Although FIG. 4 illustrates two cell strings arranged in a column direction (i.e., a +Y direction), the present disclosure is not limited thereto. That is, the two string arrangement shown in FIG. 4 is for clarity of illustration to correspond to the claimed limitation]; each second memory stack of the plurality of second memory stacks being coupled to a second word line group and having a second size [(Paragraphs 0004, 0113 and 0154-0155; FIGs. 1, 4 and 8) wherein You teaches wherein in FIG. 4, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., a +X direction). Although FIG. 4 illustrates two cell strings arranged in a column direction (i.e., a +Y direction), the present disclosure is not limited thereto. That is, the two string arrangement shown in FIG. 4 is for clarity of illustration to correspond to the claimed limitation], the second word line group comprising a plurality of second word lines stacked in the vertical direction [(Paragraphs 0004, 0113 and 0154-0155; FIGs. 1, 4 and 8) wherein You teaches wherein in FIG. 4, the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’ shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., a +X direction). Although FIG. 4 illustrates two cell strings arranged in a column direction (i.e., a +Y direction), the present disclosure is not limited thereto. That is, the two string arrangement shown in FIG. 4 is for clarity of illustration to correspond to the claimed limitation], and wherein the processor is further configured to: select a victim memory stack with a lowest ratio of a valid page count to an invalid page count from among the plurality of memory stacks [(Paragraphs 0004, 0113 and 0208; FIGs. 1, 8 and 16) wherein You teaches where the block 0 (BLK0) and block 1 (BLK1) are selected as victim blocks (Victim BLK0 and Victim BLK1). A method for selecting victim blocks may be performed based on various references. For example, memory blocks in which the amount of valid data is a certain level or less may be selected as victim blocks. Alternatively, victim blocks may be selected using a ratio of valid data to invalid data to correspond to the claimed limitation]; and copy a valid page of the victim memory stack to a target memory stack from among the plurality of memory stacks [(Paragraphs 0004, 0113 and 0205-0208; FIGs. 1, 8 and 16) wherein You teaches where the garbage collection operation may be an operation performed to secure a free block. The garbage collection operation may be an operation of copying valid data in victim blocks, also storing invalid data, to a free block and erasing the victim blocks to make them free blocks to correspond to the claimed limitation].
You does not appear to explicitly disclose the second block size being different from the first block size.
However, Muchherla discloses the second block size being different from the first block size [(Paragraphs 0042-0043; FIGs. 1 and 2B) where FIG. 2B is a further example schematic diagram of data selection from multiple sub-blocks of a wordline for performing scanning of the wordline, in accordance with some embodiments. In another embodiment, a memory portion 130B of the memory device 130 contains multiple pages corresponding to multiple sub-blocks. In one embodiment, the memory portion 130B is a more-detailed version of the memory portion 130A discussed with reference to FIG. 2A. The memory portion 130A is illustrated as having four sub-blocks (numbered 0, 1, 2, and 3 for purposes of explanation), but fewer or more sub-blocks can define multiple wordlines (WL0 . . . WL3) in different embodiments. The memory portion 130A can be understood to illustrate one implementation in which each sub-block is 16 kilobytes (KB) in size, which includes four groups of memory cells, each being 4 KB in size, but different sizes of each sub-block and each group of sub-blocks are envisioned to correspond to the claimed limitation].
You and Muchherla are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Muchherla before him or her, to modify the device of You to include the sub-blocks of Muchherla because it will enhance memory performance.
The motivation for doing so would be [“reducing the overhead costs associated with multiple reads of individual sub-blocks, and corresponding error check of each sub-block. Because at least a chunk of data is sampled form each sub-block, all of the multiple sub-blocks are effectively scanned as a set, e.g., pseudo-page” (Paragraph 0019 by Muchherla)].
You/ Muchherla does not appear to explicitly disclose a plurality of second memory stacks arranged on the plurality of first memory stacks.
However, Puthenthermadam discloses a plurality of second memory stacks arranged on the plurality of first memory stacks [(Paragraphs 0047 and 0114; FIGs. 1 and 7A) wherein when sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged vertically on top of another sub-block), erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. In addition, during the erase operation, the holes necessary for erasing one sub-block (e.g., gate-induced drain leakage (GIDL) based hole generation or holes supplied by a PWELL instead of GIDL based hole generation) can be blocked by the sub-block that is inhibited from erasing, when sub-blocks are arranged with contiguous (adjacent) word lines so that the sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged on top of another sub-block), such as what is described in FIG. 7B above, erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. For example, in FIG. 9A, a first sub-block SB0 associated with a lower tier of the stack (i.e., the first sub-block SB0 is a source side adjacent sub-block) is arranged below a second sub-block SB1 associated with an upper tier of the stack (i.e., the second sub-block SB1 is a drain side adjacent sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding with the first sub-block SB0 (selected one of the first and second blocks SB0, SB1) have a word line erase voltage VERA_WL_L1 (e.g., 0.5 volts) applied to them to encourage erasing of the memory cells connected to the word lines corresponding with the first sub-block SB0 to correspond to the claimed limitation].
You/ Muchherla and Puthenthermadam are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Puthenthermadam before him or her, to modify the device of You to include the memory stacks of Puthenthermadam because it will enhance memory buffering.
The motivation for doing so would be [“the erase speed of the selected sub-block (the one being erased) is improved” (Paragraph 0116 by Puthenthermadam)].
Therefore, it would have been obvious to combine You/ Muchherla and Puthenthermadam to obtain the invention as specified in the instant claim.
As per dependent claim 11, Muchherla discloses wherein: the first size corresponds to a number of first word lines comprised by the plurality of first word lines, and the second size corresponds to a number of second word lines comprised by the plurality of second word lines [(Paragraphs 0042-0043; FIGs. 1 and 2B) where FIG. 2B is a further example schematic diagram of data selection from multiple sub-blocks of a wordline for performing scanning of the wordline, in accordance with some embodiments. In another embodiment, a memory portion 130B of the memory device 130 contains multiple pages corresponding to multiple sub-blocks. In one embodiment, the memory portion 130B is a more-detailed version of the memory portion 130A discussed with reference to FIG. 2A. The memory portion 130A is illustrated as having four sub-blocks (numbered 0, 1, 2, and 3 for purposes of explanation), but fewer or more sub-blocks can define multiple wordlines (WL0 . . . WL3) in different embodiments. The memory portion 130A can be understood to illustrate one implementation in which each sub-block is 16 kilobytes (KB) in size, which includes four groups of memory cells, each being 4 KB in size, but different sizes of each sub-block and each group of sub-blocks are envisioned to correspond to the claimed limitation].
As per dependent claim 12, You discloses wherein: the first size corresponds to a first total number of pages comprised by each first memory stack of the plurality of first memory stacks, and the second size corresponds to a second total number of pages comprised by each second memory stack of the plurality of second memory stacks [(Paragraphs 0146, 0153, 0161-0163 and 0180; FIGs 3 and 7) where the main block may include zeroth to nth pages Page 0 to Page n. Each page may be configured with memory cells coupled to one word line. For example, memory cells coupled to a zeroth word line may constitute the zeroth page, and memory cells coupled to a first word line may constitute the first page to correspond to the claimed limitation].
Muchherla further discloses [(Paragraphs 0017-0018) where the wordline can have multiple pages on the same wordline grouped as sub-blocks. On sub-block is typically accessed at any given time. Although each sub-block has its own set of bitlines, the sub-blocks share a common page buffer or sense-amplifier. These pages are marked by sub-block boundary per wordline, and are thus referred to hereinafter as sub-blocks. Because defects can manifest themselves local to a sub-block, defect or non-defect scans are performed on each individual sub-block of a wordline].
Claims 13-15 are rejected under 35 U.S.C. 103(a) as being disclosed by You/ Muchherla, as applied to claim 10, and further in view of Saxena et al. (US PGPUB 2020/0097403 hereinafter referred to as Saxena).
As per dependent claim 13, You discloses the storage device of claim 10.
You discloses wherein the processor is further configured to: calculate, for each memory stack of the plurality of memory stacks, a difference value between the invalid page count and the valid page count [(Paragraphs 0008, 0068 and 0208-0209; FIGs 2 and 16) where the write handler 210 may select at least one of the victim blocks so as to perform the garbage collection operation. Closed blocks may Include valid data and invalid data therein. The victim block may be determined according to an amount of the valid data or the invalid data, which is included in the closed blocks. For example, memory blocks of which the amount of valid data is a certain amount or less may be selected as victim blocks among the memory blocks. The garbage collection operation of FIG. 16 may be performed through steps S1 to S3. In the step S1, block 0 (BLK0) and block 1 (BLK1) are selected as victim blocks (Victim BLK0 and Victim BLK1). A method for selecting victim blocks may be performed based on various references. For example, memory blocks in which the amount of valid data is a certain level or less may be selected as victim blocks. Alternatively, victim blocks may be selected using a ratio of valid data to invalid data to correspond to the claimed limitation].
You/ Muchherla does not appear to explicitly disclose select, as the victim memory stack, a memory stack having a largest difference value from among the plurality of memory stacks.
However, Saxena discloses select, as the victim memory stack, a memory stack having a largest difference value from among the plurality of memory stacks [(Paragraphs 0026 and 0044; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. Correlatively, a block is a logically closed block if the last write offset of the block is set to the block size, which indicates that no more additional writes are possible. Furthermore, it is noted that garbage collection operations are typically performed on closed blocks to correspond to the claimed limitation].
You/ Muchherla and Saxena are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Saxena before him or her, to modify the device of You to include the memory stacks of Saxena because it will enhance memory buffering.
The motivation for doing so would be [“provide improved sustained write performance and block endurance for NVMs due to reduced garbage collection operations” (Paragraph 0056 by Saxena)].
Therefore, it would have been obvious to combine You/ Muchherla and Saxena to obtain the invention as specified in the instant claim.
As per dependent claim 14, You discloses wherein the processor is further configured to: calculate, for each memory stack of the plurality of memory stacks, a ratio value of the valid page count to the invalid page count [(Paragraphs 0008, 0068 and 0208-0209; FIGs 2 and 16) where the write handler 210 may select at least one of the victim blocks so as to perform the garbage collection operation. Closed blocks may Include valid data and invalid data therein. The victim block may be determined according to an amount of the valid data or the invalid data, which is included in the closed blocks. For example, memory blocks of which the amount of valid data is a certain amount or less may be selected as victim blocks among the memory blocks. The garbage collection operation of FIG. 16 may be performed through steps S1 to S3. In the step S1, block 0 (BLK0) and block 1 (BLK1) are selected as victim blocks (Victim BLK0 and Victim BLK1). A method for selecting victim blocks may be performed based on various references. For example, memory blocks in which the amount of valid data is a certain level or less may be selected as victim blocks. Alternatively, victim blocks may be selected using a ratio of valid data to invalid data to correspond to the claimed limitation].
Saxena discloses select, as the victim memory stack, a memory stack with a smallest ratio value from among the plurality of memory stacks [(Paragraphs 0026, 0044 and 0055; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. The method 600 includes the invalidation factor being further based on a percentage of invalid pages that is a ratio of a number of invalid pages in a block to the total number of pages in the block. In still yet a further aspect, each of the plurality of blocks is a metablock comprising one or more physical blocks that are coupled together and configured to provide parallel write and read operations to the metablock to correspond to the claimed limitation].
As per dependent claim 15, You discloses wherein the processor is further configured to: calculate, for each memory stack of the plurality of memory stacks, a ratio value of the valid page count to a stack size [(Paragraphs 0008, 0068 and 0208-0209; FIGs 2 and 16) where the write handler 210 may select at least one of the victim blocks so as to perform the garbage collection operation. Closed blocks may Include valid data and invalid data therein. The victim block may be determined according to an amount of the valid data or the invalid data, which is included in the closed blocks. For example, memory blocks of which the amount of valid data is a certain amount or less may be selected as victim blocks among the memory blocks. The garbage collection operation of FIG. 16 may be performed through steps S1 to S3. In the step S1, block 0 (BLK0) and block 1 (BLK1) are selected as victim blocks (Victim BLK0 and Victim BLK1). A method for selecting victim blocks may be performed based on various references. For example, memory blocks in which the amount of valid data is a certain level or less may be selected as victim blocks. Alternatively, victim blocks may be selected using a ratio of valid data to invalid data to correspond to the claimed limitation].
Saxena discloses select, as the victim memory stack, a memory stack with a smallest ratio value from among the plurality of memory stacks [(Paragraphs 0026 and 0044; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. Correlatively, a block is a logically closed block if the last write offset of the block is set to the block size, which indicates that no more additional writes are possible. Furthermore, it is noted that garbage collection operations are typically performed on closed blocks to correspond to the claimed limitation].
Claim 16 is rejected under 35 U.S.C. 103(a) as being disclosed by You/ Muchherla, as applied to claim 10, and further in view of Hsiao et al. (US PGPUB 2020/0097403 hereinafter referred to as Hsiao).
As per dependent claim 16, You discloses the storage device of claim 10.
You/ Muchherla does not appear to explicitly disclose wherein the processor is further configured to: manage a garbage collection management table of the plurality of memory stacks; update the garbage collection management table according to the garbage collection operation on the plurality of memory stacks; and control the garbage collection operation on the plurality of memory stacks based on the garbage collection management table.
However, Hsiao discloses wherein the processor is further configured to: manage a garbage collection management table of the plurality of memory stacks; update the garbage collection management table according to the garbage collection operation on the plurality of memory stacks; and control the garbage collection operation on the plurality of memory stacks based on the garbage collection management table [(Paragraphs 0006, 0059 and 0067-0069; FIGs. 1, 4 and 6) where the disclosure of Hsiao provides a memory management method, capable of recording a recycled physical block subjected to the garbage collection operation into a garbage collection information table and writing the garbage collection information table into a rewritable non-volatile memory module only when the garbage collection operation is completed, and updating the garbage collection information table according to whether a plurality of recycled physical blocks recorded in the garbage collection information table are used the garbage collection management circuit unit 215 (or the recycled block stripe recording circuit 2152) calculates the total space occupied by the data tag DT, the timestamp TS, the number of the recycled block stripes TRBN and the recycled block stripe list in the currently updated garbage collection information table 400, and the difference obtained by deducting the total space size from the predetermined size is used as the size of the padding data PD. In this manner, after the padding data PD is added to the garbage collection information table 400, the total size of the garbage collection information table 400 can be made to be the predetermined size to correspond to the claimed limitation].
You/ Muchherla and Hsiao are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Hsiao before him or her, to modify the device of You to include the GC information table of Hsiao because it will enhance memory efficiency.
The motivation for doing so would be [“the operation efficiency of the storage device may be improved” (Paragraph 0009 by Hsiao)].
Therefore, it would have been obvious to combine You/ Muchherla and Hsiao to obtain the invention as specified in the instant claim.
Claim 17 is rejected under 35 U.S.C. 103(a) as being disclosed by You/ Muchherla, as applied to claim 10, in view of Hsiao et al. (US PGPUB 2020/0097403 hereinafter referred to as Hsiao), and further in view of UM et al. (US PGPUB 2016/0328155 hereinafter referred to as UM).
As per dependent claim 17, You discloses the storage device of claim 10.
You/ Muchherla does not appear to explicitly disclose wherein the processor is further configured to: manage a mapping table storing physical addresses of the non-volatile memory respectively corresponding to logical addresses received from a host.
Hsiao discloses wherein the processor is further configured to: manage a mapping table storing physical addresses of the non-volatile memory respectively corresponding to logical addresses received from a host [(Paragraphs 0041, 0059 and 0067-0069; FIGs. 1, 4 and 6) where the storage controller 210 would create a logical-to-physical address mapping table and a physical-to-logical address mapping table for recording a mapping relation between the logical addresses assigned to the rewritable non-volatile memory module 220 and the physical addresses. In other words, the storage controller 210 can look up for the physical unit mapped by one logical address by using the logical-to-physical address mapping table, and the storage controller 210 can look up for the logical address mapped by one physical address by using the physical-to-logical address mapping table. Nonetheless, the technical concept for the mapping relation between the logical addresses and the physical addresses is a well-known technical means in the field, which is not repeated hereinafter. In typical operation of storage controller, the logical-to-physical address mapping table and the physical-to-logical address mapping table may be maintained in the buffer memory 216 to correspond to the claimed limitation].
You/ Muchherla and Hsiao are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Hsiao before him or her, to modify the device of You to include the GC information table of Hsiao because it will enhance memory efficiency.
The motivation for doing so would be [“the operation efficiency of the storage device may be improved” (Paragraph 0009 by Hsiao)].
You/ Muchherla does not appear to explicitly disclose wherein to copy the valid page of the victim memory stack comprises to update the mapping table after copying the valid page of the victim memory stack to the target memory stack.
However, UM discloses and wherein to copy the valid page of the victim memory stack comprises to update the mapping table after copying the valid page of the victim memory stack to the target memory stack [(Paragraphs 0006, 0059 and 0067-0069; FIGs. 1, 4 and 6) where the erase operation unit 1348 erases the victim blocks VICTIM1 and VICTIM2 upon completion of the update of the mapping table of the storage unit 1442, which is due to the copying of the data stored in the valid pages of the victim blocks VICTIM1 and VICTIM2 to the free block FREE1. Therefore, all the pages stored in the victim blocks VICTIM1 and VICTIM2 are converted into erased states and free states through the garbage collection operation to correspond to the claimed limitation].
You/ Muchherla and Hsiao are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of You and Hsiao before him or her, to modify the device of You to include the GC information table of UM because it will enhance memory efficiency.
The motivation for doing so would be [“ memory system capable of supporting a garbage collection operation and an operating method thereof.” (Paragraph 0002 by UM)].
Therefore, it would have been obvious to combine You/ Muchherla/Hsiao and UM to obtain the invention as specified in the instant claim.
Claims 19 is rejected under 35 U.S.C. 103(a) as being disclosed by Saxena et al. (US PGPUB 2020/0097403 hereinafter referred to as Saxena), in view of Puthenthermadam et al. (US PGPUB 2022/0180948 hereinafter referred to as Puthenthermadam), in view of Muchherla et al. (US PGPUB 2022/0199184 hereinafter referred to as Muchherla).
As per independent claim 19, Saxena discloses an operating method of a processor of a storage device, the operating method comprising: selecting a victim memory stack from among first memory stacks and second memory stacks of a non-volatile memory [(Paragraphs 0026 and 0044; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. Correlatively, a block is a logically closed block if the last write offset of the block is set to the block size, which indicates that no more additional writes are possible. Furthermore, it is noted that garbage collection operations are typically performed on closed blocks to correspond to the claimed limitation]; copying a valid page of the victim memory stack to a target memory stack; wherein the selecting of the victim memory stack comprises at least one of: selecting, as the victim memory stack, a first memory stack having a smallest ratio value of a valid page count to an invalid page count from among the first memory stacks and the second memory stacks [(Paragraphs 0026, 0044 and 0055; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. The method 600 includes the invalidation factor being further based on a percentage of invalid pages that is a ratio of a number of invalid pages in a block to the total number of pages in the block. In still yet a further aspect, each of the plurality of blocks is a metablock comprising one or more physical blocks that are coupled together and configured to provide parallel write and read operations to the metablock to correspond to the claimed limitation]; selecting, as the victim memory stack, a second memory stack having a largest difference value between the invalid page count and the valid page count from among the first memory stacks and the second memory stacks; or selecting, as the victim memory stack, a third memory stack having a smallest ratio value of the valid page count to a block size from among the first memory stacks and the second memory stacks [(Paragraphs 0026 and 0044; FIGs. 1, 2 and 6) wherein the victim block selection process includes a process illustrated in block 206 of searching a closed block pool. This search is an iterative process in which a data storage device controller (e.g., controller 108 in FIG. 1), for example, and more particularly a garbage collector circuit (e.g., circuit 118) sequentially examines each of the closed blocks in the closed block pool by determining whether a minimum valid page count (MinValidPageCount or MinVPC) is less than a current MinVPC as illustrated by decision block 208. The purpose of this examination is to determine which block in the pool of blocks has lowest valid page count. Each time the decision at block 208 finds a block having a MinVPC less than the current MinVPC, the MinVPC value is updated as shown by block 210. It is noted here that a closed block pool is a collection of blocks (e.g., closed blocks) that have been termed as physically or logically closed. A block is physically closed if all the pages in the blocks have been written or the block has been fully programmed. Correlatively, a block is a logically closed block if the last write offset of the block is set to the block size, which indicates that no more additional writes are possible. Furthermore, it is noted that garbage collection operations are typically performed on closed blocks to correspond to the claimed limitation].
Saxena does not appear to explicitly disclose performing an erase operation on the victim memory stack, the first memory stacks being on a substrate, the second memory stacks being on the first memory stacks, each of the first memory stacks having a first size, each of the second memory stacks having a second size.
However, Puthenthermadam discloses performing an erase operation on the victim memory stack, the first memory stacks being on a substrate, the second memory stacks being on the first memory stacks, each of the first memory stacks having a first size, each of the second memory stacks having a second size [(Paragraphs 0047 and 0114; FIGs. 1 and 7A) wherein when sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged vertically on top of another sub-block), erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. In addition, during the erase operation, the holes necessary for erasing one sub-block (e.g., gate-induced drain leakage (GIDL) based hole generation or holes supplied by a PWELL instead of GIDL based hole generation) can be blocked by the sub-block that is inhibited from erasing, when sub-blocks are arranged with contiguous (adjacent) word lines so that the sub-blocks are arranged vertically in a stack (e.g., one or more sub-blocks arranged on top of another sub-block), such as what is described in FIG. 7B above, erasing one sub-block can cause erase disturb in another sub-block that is inhibited from erasing. For example, in FIG. 9A, a first sub-block SB0 associated with a lower tier of the stack (i.e., the first sub-block SB0 is a source side adjacent sub-block) is arranged below a second sub-block SB1 associated with an upper tier of the stack (i.e., the second sub-block SB1 is a drain side adjacent sub-block). During an erase operation of the first sub-block SB0, an erase voltage VERA is applied to the substrate or channel of the block. At the same time, the word lines corresponding with the first sub-block SB0 (selected one of the first and second blocks SB0, SB1) have a word line erase voltage VERA_WL_L1 (e.g., 0.5 volts) applied to them to encourage erasing of the memory cells connected to the word lines corresponding with the first sub-block SB0 to correspond to the claimed limitation].
Saxena and Puthenthermadam are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Saxena and Puthenthermadam before him or her, to modify the device of Saxena to include the memory stacks of Puthenthermadam because it will enhance memory buffering.
The motivation for doing so would be [“the erase speed of the selected sub-block (the one being erased) is improved” (Paragraph 0116 by Puthenthermadam)].
Saxena does not appear to explicitly disclose the second block size being different from the first block size.
However, Muchherla discloses the second block size being different from the first block size [(Paragraphs 0042-0043; FIGs. 1 and 2B) where FIG. 2B is a further example schematic diagram of data selection from multiple sub-blocks of a wordline for performing scanning of the wordline, in accordance with some embodiments. In another embodiment, a memory portion 130B of the memory device 130 contains multiple pages corresponding to multiple sub-blocks. In one embodiment, the memory portion 130B is a more-detailed version of the memory portion 130A discussed with reference to FIG. 2A. The memory portion 130A is illustrated as having four sub-blocks (numbered 0, 1, 2, and 3 for purposes of explanation), but fewer or more sub-blocks can define multiple wordlines (WL0 . . . WL3) in different embodiments. The memory portion 130A can be understood to illustrate one implementation in which each sub-block is 16 kilobytes (KB) in size, which includes four groups of memory cells, each being 4 KB in size, but different sizes of each sub-block and each group of sub-blocks are envisioned to correspond to the claimed limitation].
Saxena and Muchherla are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Saxena and Muchherla before him or her, to modify the device of Byun to include the sub-blocks of Muchherla because it will enhance memory performance.
The motivation for doing so would be [“reducing the overhead costs associated with multiple reads of individual sub-blocks, and corresponding error check of each sub-block. Because at least a chunk of data is sampled form each sub-block, all of the multiple sub-blocks are effectively scanned as a set, e.g., pseudo-page” (Paragraph 0019 by Muchherla)].
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 9, but would be allowable if rewritten as independent claims.
The reason for allowance of claim 9 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 9, the limitations of “wherein the performing of the first garbage collection operation further comprises: selecting the first victim sub-block with the lowest valid page count from among a plurality of first sub-blocks, when the lowest valid page count is greater than or equal to a threshold value, and selecting the first victim sub-block with a highest invalid page count from among the plurality of first sub-blocks, when the highest valid page count is less than the threshold value, wherein the threshold value changes based on at least one of a program/erase cycle count or a page migration time of each first sub-block of the plurality of first sub-blocks, and wherein the page migration time corresponds to a sum of program time, read time and erase time”.
The reason for allowance of claim 18 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 18, the limitations of “wherein the processor is further configured to: select the victim memory stack with a lowest valid page count from among the plurality of memory stacks, when the valid page count is greater than or equal to a threshold value, and select the victim memory stack with a highest invalid page count from among the plurality of memory stacks, when the valid page count is less than the threshold value, wherein the threshold value changes based on at least one of a program/erase cycle count or a page migration time of each memory stack of the plurality of memory stacks, and wherein the page migration time corresponds to a sum of program time, read time and erase time”.
The reason for allowance of claim 20 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 20, the limitations of “wherein the selecting of the victim memory stack further comprises: selecting the victim memory stack with a lowest valid page count from among the first memory stacks and the second memory stacks, when the valid page count is greater than or equal to a threshold value, and selecting the victim memory stack with a highest invalid page count from among the first memory stacks and the second memory stacks, when the valid page count is less than the threshold value, wherein the threshold value changes based on at least one of a program/erase cycle count or a page migration time of each memory stack of the first memory stacks and the second memory stacks, and wherein the page migration time corresponds to a sum of program time, read time and erase time”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al., US PGPUB 2022/0261344 – teaches GARBAGE COLLECTION OPERATION MANAGEMENT.
Conclusion
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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