DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 5-7, and 9-18 have been considered but are moot in light of the new grounds of rejection set forth below, necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 6, 11-12, 15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Matsushita et al. (US Pat. App. Pub. No. 2021/0335542) in view of Lee et al. (US Pat. App. Pub. No. 2022/0189700).
With respect to claim 1, Matsushita teaches a multilayer electronic component (see the abstract), comprising: a body including a dielectric layer and internal electrodes alternately disposed with the dielectric layer (see FIGS. 13 and 2, internal electrodes 12 and 13, and dielectric 15, and paragraphs [0113], noting that the embodiment of FIG. 13 shares the same constituent elements as FIGS. 1-6, aside from the configuration of the protrusions 28, and [0045]-[0047]), and including a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first and second surfaces and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to fourth surfaces and opposing each other in a third direction (see FIGS. 1 and 13, and paragraph [0043]); and external electrodes including central portions disposed on centers of the third and fourth surfaces (see FIG. 13, external electrode 24), respectively, and outer portions connected to the central portions and disposed on outer regions of the third and fourth surfaces (see FIG. 13, regions 28a/28b), respectively, wherein each of the external electrodes includes a lower electrode layer disposed in the central portion and the outer portion and in contact with one of the internal electrodes (see FIG. 13, layer 24), and an upper electrode layer disposed in the outer portion and disposed on the lower electrode layer (see FIG. 13, layers 28a/28b, and wherein, when a maximum size in the second direction of the central portion is defined as Le1 and a maximum size in the second direction of the outer portion is defined as Le2, Le2>Le1 is satisfied (see FIG. 13), wherein the upper electrode layer includes a first electrode layer disposed on one end in the first direction of the third and fourth surfaces, and a second electrode layer disposed on the other end in the first direction of the third and fourth surfaces, wherein the first and second electrode layers are spaced apart from each other and extend in the third direction (see FIG. 13, elements 28b, disposed apart from each other), wherein each of the external electrodes includes a first band portion extending from the outer portion to a portion of the first surface (see FIG. 13, noting that element 24 includes a band portion on the top surface), and a second band portion extending from the outer portion to a portion of the second surface (see FIG. 13, noting that element 24 includes a band portion on the bottom surface), wherein first and second ends of the lower electrode layer are disposed in the first and second band portions, respectively (see FIG. 13).
Matsushita fails to teach that the first electrode layer of the upper electrode layer does not cover the first end of the lower electrode layer disposed in the first band portion, and the second electrode layer of the upper electrode layer does not cover the second end of the lower electrode layer disposed in the second band portion.
Lee, on the other hand, teaches the first electrode layer of the upper electrode layer does not cover the first end of the lower electrode layer disposed in the first band portion, and the second electrode layer of the upper electrode layer does not cover the second end of the lower electrode layer disposed in the second band portion. See FIG. 5, where layer 131a2 does not cover the ends of layer 131a1; see also, paragraph [0090]. Such an arrangement helps improve moisture resistance reliability of the electronic component. See paragraph [0091].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Matsushita, as taught by Lee, in order to improve the moisture resistance reliability of the electronic component.
With respect to claim 2, the combined teachings of Matsushita and Lee teach that a boundary between the central portion and the outer portion corresponds to an end of the upper electrode layer adjacent to the central portion. See FIG. 13 of Matsushita.
With respect to claim 6, the combined teachings of Matsushita and Lee teach that, when a maximum size in the first direction of the multilayer electronic component is defined as Tm and a size in the first direction of the central portion is defined as Tc, a ratio of Tc to Tm (Tc/Tm) is 0.5 or more. See Matsushita, paragraph [0064].
With respect to claim 11, the combined teachings of Matsushita and Lee teach that the upper electrode layer is disposed to surround the central portion. See Matsushita, FIG. 13.
With respect to claim 12, the combined teachings of Matsushita and Lee teach that the upper electrode layer is disposed to completely surround the central portion. See Matsushita, FIG. 13.
With respect to claim 15, the combined teachings of Matsushita and Lee teach that at least a portion of the outer portion convexly protrudes more outwardly than the central portion. See Matsushita, FIG. 13.
With respect to claim 17, the combined teachings of Matsushita and Lee teach a printed circuit board (see Matsushita, FIG. 6, element 100 and paragraph [0069]) comprising a plurality of pads disposed on one surface thereof (see Matsushita, FIG. 6, elements 52 and paragraph [0071]), the multilayer electronic component of claim 3 mounted on the plurality of pads (see Matsushita, FIG. 6), and a solder connecting the plurality of pads to the multilayer electronic component (see Matsushita, FIG. 6, element 60 and paragraph [0074]).
With respect to claim 18, the combined teachings of Matsushita and Lee teach that the solder is disposed between the band portion and the pad and extends along an outer surface of the upper electrode layer to be in contact with a portion of the central portion. See Matsushita, FIG. 5, noting that solder 60 is disposed between the band portion and the pad and extends to the central portion of the external electrode.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Matsushita et al. (US Pat. App. Pub. No. 2021/0335542) in view of Lee et al. (US Pat. App. Pub. No. 2022/0189700), and further, in view of Fukuma et al. (US Pat. App. Pub. No. 2021/0020378).
With respect to claim 7, the combined teachings of Matsushita and Lee fail to teach that the lower electrode layer has a maximum thickness in the central portion and a minimum thickness in the outer portion.
Fukuma, on the other hand, teaches that the lower electrode layer has a maximum thickness in the central portion and a minimum thickness in the outer portion. See FIG. 2, element 160 and paragraph [0030]. Such an arrangement results is part of a capacitor having improved moisture resistance. See paragraph [0006].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Fukuma, in order to improve the moisture resistance of the capacitor.
With respect to claim 16, the combined teachings of Matsushita and Lee fail to teach that the central portion is convex outwardly.
Fukuma, on the other hand, teaches that the central portion is convex outwardly. See FIG. 2, element 160 and paragraph [0030]. Such an arrangement results is part of a capacitor having improved moisture resistance. See paragraph [0006].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Fukuma, in order to improve the moisture resistance of the capacitor.
Claims 9, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsushita et al. (US Pat. App. Pub. No. 2021/0335542) in view of Lee et al. (US Pat. App. Pub. No. 2022/0189700), and further, in view of Cho (US Pat. App. Pub. No. 2022/139626).
With respect to claim 9, the combined teachings of Matsushita and Lee fail to teach that the upper electrode layer includes first to fourth corner electrode layers disposed on corners of the third and fourth surfaces and spaced apart from each other.
Cho, on the other hand, teaches that the upper electrode layer includes first to fourth corner electrode layers disposed on corners of the third and fourth surfaces and spaced apart from each other. See FIG. 8. Such an arrangement results in improved durability against deformation of the board, while preventing an increase in ESR. See paragraph [0100].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Cho, in order to improve durability against deformation and preventing an increase in ESR.
With respect to claim 10, the combined teachings of Matsushita, Lee, and Cho fail to explicitly teach that, when a maximum size in the third direction of the multilayer electronic component is defined as Wm, a minimum distance in the third direction between the first corner electrode layer and the second corner electrode layer or a minimum distance in the third direction between the third corner electrode layer and the fourth corner electrode layer is defined as We, a ratio of We to Wm (We/Wm) is 0.8 or lower.
However, such a modification is considered to be a mere change in size/proportion, which has been found to be obvious as being well-within the purview of one of ordinary skill in the art. See MPEP 2144.04(IV)(A), citing In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) and Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984).
With respect to claim 14, the combined teachings of Matsushita and Lee fail to teach that the upper electrode layer includes a metal and resin.
Cho, on the other hand, teaches that that the upper electrode layer includes a metal and resin. See FIG. 8 and paragraph [0117]. Such an arrangement results in improved durability against deformation of the board, while preventing an increase in ESR. See paragraph [0100].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Cho, in order to improve durability against deformation and preventing an increase in ESR.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Matsushita et al. (US Pat. App. Pub. No. 2021/0335542) in view of Lee et al. (US Pat. App. Pub. No. 2022/0189700), and further, in view of Lee et al. (US Pat. App. Pub. No. 2016/0005539).
With respect to 5, the combined teachings of Matsushita and Lee fail to explicitly teach that, when a maximum size in the second direction of the multilayer electronic component measured at the central portion is defined as Lm1, and a maximum size in the second direction of the multilayer electronic component measured at the outer portion is defined as Lm2, 0.01≤(Lm2-Lm1)/Lm1≤0.05 is satisfied.
However, Lee ‘539 teaches that a ratio of thickness of the thicker electrode portion to the thinner electrode portion is 1.5 to 4. See paragraph [0061]. Such an arrangement results in an improved mounting stability while maintaining an appropriate capacitance implementation area. See paragraph [0064]. Thus, Lee establishes that the thickness of the thicker electrode portion is a result-oriented variable that can be optimized by one of ordinary skill in the art. See MPEP 2144.059(II)(A) and (II)(B), citing In re Aller, 220F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) and In re Stepan, 868 F.3d 1342, 1346, 123 USPQ2d 1838, 1841 (Fed. Cir. 2017).
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Lee ‘539, in order to improve mounting stability while maintaining an appropriate capacitance implementation area.
With respect to claim 13, the combined teachings of Matsushita and Lee fail to teach that the upper electrode layer includes a metal and glass.
Lee ‘539, on the other hand, teaches that the upper electrode layer includes a metal and glass. See FIG. 2 and paragraph [0082]. Such an arrangement is well known for forming an external electrode connected to the internal electrodes. See paragraph [0056].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Matsushita and Lee, as taught by Lee ‘539, in order to form an external electrode connected to the internal electrodes.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole, can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DION R. FERGUSON/Primary Examiner, Art Unit 2847
Prosecution Insights