DETAILED ACTION
This Office Action, based on application 18/965,377, is responsive to applicant’s initial filing on 2 December 2024. Claims 1-20, as originally filed, are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2 December 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The following claims are objected to due to informalities:
Claim 17: “wherein each physical block of the plurality of physical blocks comprises at least two multiple erase blocks that are independently erasable, and wherein the multiple erase blocks …” should be “wherein each physical block of the plurality of physical blocks comprises at least two at least two
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 9-13, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIURA (US PGPub 2018/0108404) in further view of NAZARIAN et al (US PGPub 2007/0247910).
With respect to Claim 1, MIURA discloses an apparatus, comprising:
a memory array (Fig 1, NVM0; ¶[0062] – “Each of the nonvolatile memory modules NVMD0 … includes nonvolatile memory devices NVM0 …”); and
a controller coupled to the memory array (Fig 1, NVM-CTL; ¶[0062] – “Each of the nonvolatile memory modules NVM0 … includes … a control circuit NVM-CTL that controls these nonvolatile memory devices …”) and configured to:
perform a memory management operation at an erase block level; and
switch to perform the memory management operation at a physical block level (¶[0027] – “This control circuit dynamically changes a size of an erase unit block including the physical address associated with the logical address based on an access state with respect to the logical address”; Fig 9 – Step 4 – “Decide block size with respect to each logical address dlad”; ¶[0032] – “The control circuit performs write by calculating a frequency of access to a logical address of a write request input from the outside within a certain period, and changing a block size of the nonvolatile memory based on this access frequency … Accordingly, a data copy amount at the time of garbage collection decreases”; Fig 9 illustrates Step 4 is performed responsive to the elapse of a valid period TC – performance of a first garbage collection during a first TC based on a first block size and performance of a second garbage collection during a second TC based on a second block size is analogous to applicant’s claimed “perform a memory management operation … and switch to perform the memory management operation …”).
MIURA may not explicitly disclose the memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block.
However, NAZARIAN discloses the memory array (Fig 4, Array 430) comprising a plurality of physical blocks of strings of memory cells (¶ [0026] – “The memory device includes an array of memory cells 430 having superNAND strings such as strings 100, 200, or 300 described above”), wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable (Abstract – “A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure”), and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block (Abstract – “the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string”).
MIURA and NAZARIAN are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA and NAZARIAN before him or her, to modify the solid state drives of MIURA to include separator elements in NAND strings as taught by NAZARIAN. A motivation for doing so would have been to allow for the maintenance of erase block sizes while increasing the string size (¶[0024]). Therefore, it would have been obvious to combine MIURA and NAZARIAN to obtain the invention as specified in the instant claims.
With respect to Claim 11, MIURA discloses an apparatus, comprising:
a memory array (Fig 1, NVM0; ¶[0062] – “Each of the nonvolatile memory modules NVMD0 … includes nonvolatile memory devices NVM0 …”); and
a controller coupled to the memory array (Fig 1, NVM-CTL; ¶[0062] – “Each of the nonvolatile memory modules NVM0 … includes … a control circuit NVM-CTL that controls these nonvolatile memory devices …”) and configured to:
track a program/erase (P/E) cycling offset for the multiple erase blocks (¶[0022] – “The erase count for each block is managed using an erase count table and the like”);
perform garbage collection on a per erase block basis; and
periodically switch to perform garbage collection on a per physical block basis instead of on a per erase block basis (¶[0027] – “This control circuit dynamically changes a size of an erase unit block including the physical address associated with the logical address based on an access state with respect to the logical address”; Fig 9 – Step 4 – “Decide block size with respect to each logical address dlad”; ¶[0032] – “The control circuit performs write by calculating a frequency of access to a logical address of a write request input from the outside within a certain period, and changing a block size of the nonvolatile memory based on this access frequency … Accordingly, a data copy amount at the time of garbage collection decreases”; Fig 9 illustrates Step 4 is performed responsive to the elapse of a valid period TC – performance of a first garbage collection during a first TC based on a first block size and performance of a second garbage collection during a second TC based on a second block size is analogous to applicant’s claimed “perform garbage collection … and switch to perform garbage collection …”).
MIURA may not explicitly disclose the memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block.
However, NAZARIAN discloses the memory array (Fig 4, Array 430) comprising a plurality of physical blocks of strings of memory cells (¶ [0026] – “The memory device includes an array of memory cells 430 having superNAND strings such as strings 100, 200, or 300 described above”), wherein each physical block of the plurality of physical blocks comprises multiple erase blocks that are independently erasable (Abstract – “A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure”), and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block (Abstract – “the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string”).
MIURA and NAZARIAN are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA and NAZARIAN before him or her, to modify the solid state drives of MIURA to include separator elements in NAND strings as taught by NAZARIAN. A motivation for doing so would have been to allow for the maintenance of erase block sizes while increasing the string size (¶[0024]). Therefore, it would have been obvious to combine MIURA and NAZARIAN to obtain the invention as specified in the instant claims.
With respect to Claim 17, MIURA discloses a method, comprising:
tracking a program/erase (P/E) cycling offset (¶[0022] – “The erase count for each block is managed using an erase count table and the like”) for multiple erase blocks of a memory array (Fig 1, NVM0; ¶[0062] – “Each of the nonvolatile memory modules NVMD0 … includes nonvolatile memory devices NVM0 …”);
performing garbage collection on a per erase block basis; and
periodically switching to performing garbage collection on a per physical block basis instead of on a per erase block basis (¶[0027] – “This control circuit dynamically changes a size of an erase unit block including the physical address associated with the logical address based on an access state with respect to the logical address”; Fig 9 – Step 4 – “Decide block size with respect to each logical address dlad”; ¶[0032] – “The control circuit performs write by calculating a frequency of access to a logical address of a write request input from the outside within a certain period, and changing a block size of the nonvolatile memory based on this access frequency … Accordingly, a data copy amount at the time of garbage collection decreases”; Fig 9 illustrates Step 4 is performed responsive to the elapse of a valid period TC – performance of a first garbage collection during a first TC based on a first block size and performance of a second garbage collection during a second TC based on a second block size is analogous to applicant’s claimed “perform garbage collection … and switch to perform garbage collection …”).
MIURA may not explicitly disclose the memory array comprising a plurality of physical blocks of strings of memory cells, wherein each physical block of the plurality of physical blocks comprises at least two multiple erase blocks that are independently erasable, and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block.
However, NAZARIAN discloses the memory array (Fig 4, Array 430) comprising a plurality of physical blocks of strings of memory cells (¶ [0026] – “The memory device includes an array of memory cells 430 having superNAND strings such as strings 100, 200, or 300 described above”), wherein each physical block of the plurality of physical blocks comprises at least two multiple erase blocks that are independently erasable (Abstract – “A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure”), and wherein the multiple erase blocks within a particular physical block comprise memory cells coupled to a same string corresponding to the particular physical block (Abstract – “the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string”).
MIURA and NAZARIAN are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA and NAZARIAN before him or her, to modify the solid state drives of MIURA to include separator elements in NAND strings as taught by NAZARIAN. A motivation for doing so would have been to allow for the maintenance of erase block sizes while increasing the string size (¶[0024]). Therefore, it would have been obvious to combine MIURA and NAZARIAN to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
MIURA further discloses wherein the memory management operation is a garbage collection operation (¶[0151] – “The feature of write is that a copy amount of the garbage collection decreases in the case of performing access focusing on a small block as described above. On the other hand, the read performance is improved in the read access in which data is arranged to be dispersed in the nonvolatile memory. Accordingly, it is more desirable to consider both the features in order to obtain a performance balance”).
With respect to Claim 3, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
MIURA further discloses wherein the controller is configured to switch between performing the memory management operation at the erase block level and at the physical block level in accordance with a memory management policy that includes a particular frequency at which the memory management operation is performed at the physical block level (¶[0122] – “In the flow of Fig 9, measurement of a valid period TC is first started in Step 0. The valid period is a sampling period for analysis of a feature of access”; Fig 9 – implementation of Step 4 to decide block sizes for each sampling period analogous to ‘a particular frequency’).
With respect to Claim 4, the combination of MIURA and NAZARIAN disclose the apparatus of claim 3.
MIURA further discloses wherein the particular frequency is a fixed frequency (¶[0122] – “In the flow of Fig 9, measurement of a valid period TC is first started in Step 0. The valid period is a sampling period for analysis of a feature of access”; Fig 9 – implementation of Step 4 to decide block sizes for each sampling period analogous to ‘a particular frequency’).
With respect to Claim 5, the combination of MIURA and NAZARIAN disclose the apparatus of claim 3.
MIURA further discloses wherein the particular frequency is a variable frequency (¶[0122] – “In the flow of Fig 9, measurement of a valid period TC is first started in Step 0. The valid period is a sampling period for analysis of a feature of access”; Fig 9 – implementation of Step 4 to decide block sizes for each sampling period analogous to ‘a particular frequency’), and wherein the variable frequency is a function of an erase block program/erase (P/E) cycling offset value associated with the memory array (Fig 12 – Step 4 - block sizes are determined based on WCRATE calculated in Fig 11 – Step 3 – WCRATE is calculated based on write access count).
With respect to Claim 9, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
NAZARIAN further discloses wherein each physical block of the memory array comprises at least three erase blocks that are independently erasable (¶[0019] – “a divider element is placed every 32 cells in a NAND string that is larger than 32 cells … in a NAND structure with 128 cells, three divider elements are used to divide the 128 cell NAND string into four sub-strings of 32 cells each”).
With respect to Claim 10, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
MIURA further discloses wherein the memory array comprises a three-dimensional replacement gate NAND array (¶[0209] – the nonvolatile memory may have a three-dimensional structure).
With respect to Claim 12, the combination of MIURA and NAZARIAN disclose the apparatus of claim 11.
MIURA further discloses wherein a frequency at which the controller periodically switches to perform garbage collection on the per physical block basis is variable (¶[0122] – “In the flow of Fig 9, measurement of a valid period TC is first started in Step 0. The valid period is a sampling period for analysis of a feature of access”; Fig 9 – implementation of Step 4 to decide block sizes for each sampling period analogous to ‘a particular frequency’).
With respect to Claim 13, the combination of MIURA and NAZARIAN disclose the apparatus of claim 12.
MIURA further discloses wherein the frequency is a function of the P/E cycling offset (Fig 12 – Step 4 - block sizes are determined based on WCRATE calculated in Fig 11 – Step 3 – WCRATE is calculated based on write access count)
With respect to Claim 19, the combination of MIURA and NAZARIAN disclose the method of claim 17. MIURA further discloses after switching to performing garbage collection on the per physical block basis instead of on the per erase block basis, switching back to performing garbage collection on the per erase block basis (¶[0027] – “This control circuit dynamically changes a size of an erase unit block including the physical address associated with the logical address based on an access state with respect to the logical address”; Fig 9 – Step 4 – “Decide block size with respect to each logical address dlad”; ¶[0032] – “The control circuit performs write by calculating a frequency of access to a logical address of a write request input from the outside within a certain period, and changing a block size of the nonvolatile memory based on this access frequency … Accordingly, a data copy amount at the time of garbage collection decreases”; Fig 9 illustrates Step 4 is performed responsive to the elapse of a valid period TC – performance of a first garbage collection during a first TC based on a first block size and performance of a second garbage collection during a second TC based on a second block size is analogous to applicant’s claimed “perform garbage collection … and switch to perform garbage collection …”).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIURA in further view of NAZARIAN and KANNO (US PGPub 2018/0088805).
With respect to Claim 7, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
MIURA and NAZARIAN may not explicitly disclose wherein the controller is configured to switch between performing the memory management operation at the erase block level and at the physical block level based on a target latency associated with execution of commands received from a host.
However, KANNO discloses wherein the controller is configured to switch between performing the memory management operation at the erase block level and at the physical block level based on a target latency associated with execution of commands received from a host (¶[0108] – “the amount of data required to be copied for the garbage collection increases as the block size increases”).
MIURA, NAZARIAN, and KANNO are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and KANNO before him or her, to modify the block sizes determined during a valid period of the combination of MIURA and NAZARIAN to include sizing blocks based on controlling write latency as taught by KANNO. A motivation for doing so would have been to recognize that having larger sub-blocks increases the amount of data required to be copied for garbage collection and subsequently increases write latency since write latency indicates a response time required in writing data (¶[0106]); thus, controlling sub-blocks in units of a minimum data size enables write operations to be performed at a stable latency. Therefore, it would have been obvious to combine MIURA, NAZARIAN, and KANNO to obtain the invention as specified in the instant claims.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIURA in further view of NAZARIAN and YANG (US PGPub 2023/0041476).
With respect to Claim 15, the combination of MIURA and NAZARIAN disclose the apparatus of claim 11.
MIURA and NAZARIAN may not explicitly disclose wherein at least one of the physical blocks includes a number of dummy word lines separating at least two multiple erase blocks within the at least one physical block.
However, YANG discloses wherein at least one of the physical blocks includes a number of dummy word lines separating at least two multiple erase blocks within the at least one physical block (¶[0108] – “The conductive layers connected to control gates of dummy memory cells are referred to as dummy word lines”).
MIURA, NAZARIAN, and YANG are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and YANG before him or her, to modify the separator elements of the combination of MIURA and NAZARIAN to include conductive layers as taught by YANG. A motivation for doing so would have been to set word line layers adjacent to an interface region as dummy word lines since the layers suffer from edge effects such as difficulty in programming or erasing (¶[0118]). Therefore, it would have been obvious to combine MIURA, NAZARIAN, and YANG to obtain the invention as specified in the instant claims.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIURA in further view of NAZARIAN and SZUBBOCSEV (US PGPub 2017/0286286).
With respect to Claim 8, the combination of MIURA and NAZARIAN disclose the apparatus of claim 1.
MIURA and NAZARIAN may not explicitly disclose wherein the controller is configured to switch between performing the memory management operation at the erase block level and at the physical block level based on a workload.
However, SZUBBOCSEV discloses wherein the controller is configured to switch between performing the memory management operation at the erase block level and at the physical block level based on a workload (¶[0039] – “different sets of rules for constructing different superblocks may be employed depending on the size of superblock needed for a given garbage collection operation”).
MIURA, NAZARIAN, and SZUBBOCSEV are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and SZUBBOCSEV before him or her, to modify the block sizes determined during a valid period of the combination of MIURA and NAZARIAN to include sizing blocks based on determining the number of blocks needed to be cleared during a garbage collection process {analogous to a ‘workload’} as taught by SZUBBOCSEV. A motivation for doing so would have been to satisfy the free space requirements needed for a garbage collection process (¶[0039]). Therefore, it would have been obvious to combine MIURA, NAZARIAN, and SZUBBOCSEV to obtain the invention as specified in the instant claims.
With respect to Claim 16, the combination of MIURA and NAZARIAN disclose the apparatus of claim 11.
MIURA and NAZARIAN may not explicitly disclose wherein the controller is configured to selectively perform the garbage collection on the per physical block basis based on an amount of valid data on a per physical block basis (¶[0032] – “additional combinations of blocks and dies are also contemplated as embodiments of the disclosure, which may depend, in part, on the size of the dynamically constructed superblock. For example, constructing a dynamic superblock to include six physical blocks may cause the FTL to add block 3 of the second die and block 3 of the third die as they have the next lowest valid data for each respective channel”).
However, SZUBBOCSEV discloses wherein the controller is configured to selectively perform the garbage collection on the per physical block basis based on an amount of valid data on a per physical block basis.
MIURA, NAZARIAN, and SZUBBOCSEV are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and SZUBBOCSEV before him or her, to modify the block sizes determined during a valid period of the combination of MIURA and NAZARIAN to include constructing superblocks based on the amount of valid data in blocks as taught by SZUBBOCSEV. A motivation for doing so would have been to minimize the amount of valid data that needs to be relocated during a garbage collection process thus improving performance of garbage collection (¶[0003]). Therefore, it would have been obvious to combine MIURA, NAZARIAN, and SZUBBOCSEV to obtain the invention as specified in the instant claims.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIURA in further view of NAZARIAN and KUEHNE (US PGPub 2011/0055458).
With respect to Claim 18, the combination of MIURA and NAZARIAN disclose the method of claim 17.
MIURA and NAZARIAN may not explicitly disclose switching to performing garbage collection on the per physical block basis instead of on the per erase block basis responsive to identifying a sequential workload..
However, KUEHNE discloses switching to performing garbage collection on the per physical block basis instead of on the per erase block basis responsive to identifying a sequential workload (¶[0138] – “Having larger sub-blocks improves sequential write”).
MIURA, NAZARIAN, and KUEHNE are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and KUEHNE before him or her, to modify the block sizes determined during a valid period of the combination of MIURA and NAZARIAN to include sizing blocks based on determining sequential workloads as taught by KUEHNE. A motivation for doing so would have been to recognize that having larger sub-blocks improves sequential writes and worsens random writes (¶[0138]); thus, sequential write performance may be optimized. Therefore, it would have been obvious to combine MIURA, NAZARIAN, and KUEHNE to obtain the invention as specified in the instant claims.
With respect to Claim 20, the combination of MIURA and NAZARIAN disclose the method of claim 19.
MIURA and NAZARIAN may not explicitly disclose switching back to performing garbage collection on the per erase block basis responsive to a determined change in a quality of service.
However, KUEHNE discloses switching back to performing garbage collection on the per erase block basis responsive to a determined change in a quality of service (¶[0138] – “Having larger sub-blocks improves sequential writes and worsens random writes” – likewise, smaller sub-blocks improve random writes while worsening sequential writes).
MIURA, NAZARIAN, and KUEHNE are analogous art because they are from the same field of endeavor of memory array management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MIURA, NAZARIAN, and KUEHNE before him or her, to modify the block sizes determined during a valid period of the combination of MIURA and NAZARIAN to include sizing blocks based on determining sequential or random workloads as taught by KUEHNE. A motivation for doing so would have been to recognize that having smaller sub-blocks improves random writes and worsens sequential writes (¶[0138]); thus, sub-blocks configured for sequential writes may be reconfigured for random writes responsive to determining a change in write patterns in order to optimize random write performance and likewise improve quality of service. Therefore, it would have been obvious to combine MIURA, NAZARIAN, and KUEHNE to obtain the invention as specified in the instant claims.
Allowable Subject Matter
Claims 6 and 14 are allowed.
Claim 6 (and similarly Claim 14) is directed to configuring a memory controller to switch between ‘physical’ and ‘erase’ block levels (e.g. configurations or sizes) when performing a memory management operation. The claim is further limited to perform the switching based on (1) a function of an erase block program/erase (P/E) cycling offset value of the memory array, and (2) a function of the amount of valid data per physical block. The Office maintains (a) the switching between different block levels is disclosed in cited prior art including the combination of MIURA and NAZARIAN, (b) the switching may be based on a P/E cycling offset value as further disclosed in MIURA, and (c) the switching may be based on the amount of valid data per physical block as disclosed in cited prior art including SZUBBOCSEV. However, cited prior art has not been found to anticipate or render obvious the switching between ‘physical’ and ‘erase’ block levels based on a function including both (b) and (c) as limited in the claim.
Claims 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The Office would like to emphasize that while one or more reasons are offered as to why the claims are allowable over the prior art, it is each claim, taken as a whole, including interrelationships and interconnections between various claimed elements which are allowable over the prior art of record and not any individual limitation of a claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach related methods for configuring block sizes to optimize garbage collection in memories.
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/ERIC T LOONAN/Examiner, Art Unit 2137