DETAILED ACTION
1. This action is in response to the application filed on 12/2/24.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “during a delayed time when the second transistor is disconnected…; and when the voltage of the second node is adjusted to a first voltage level, disconnect the second transistor”. This is unclear, because the second transistor is already disconnected during the delayed time. Therefore, how is the second transistor disconnecting again when the voltage adjusted to the first voltage level?
Claims 10-20 are rejected due to their dependency of claim 9.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Popovici et al. (US 20140218973).
Regarding claim 1: Popovici et al. disclose (i.e. figures 3 and 7) a method of controlling a converting device (i.e. 300), the method comprising:
connecting a first transistor (i.e. Q1) coupled to a first node (i.e. N1) and a second transistor (i.e. Q2) coupled to a second node (i.e. N2) to generate a primary current (i.e. Ip) flowing from the first node (i.e. N1) through a primary coil (i.e. 320) to the second node (i.e. N2);
generating a secondary current (i.e. IS) according to the primary current (i.e. Ip) to supply power to a load (i.e. 308); and
performing one of: during a delayed time (i.e. time of DBBM at t2-t2’) when the second transistor (i.e. Q2) is disconnected (i.e. Off), discharging the second node (i.e. N2) by the second transistor (i.e. Q2) to decrease a voltage (i.e. voltage at N2 when Q2 is turn off during the delayed time) of the second node (i.e. N2); and
when the voltage of the second node is adjusted to a first voltage level, disconnecting the second transistor; or during the delayed time (i.e. time of DBBM at t2-t2’) when the second transistor (i.e. Q2) is disconnected (i.e. Off), charging the second node (i.e. N2) by the first transistor (i.e. Q1, figure 7: signal ZVS1) (i.e. ¶ 28-31 and 47-50).
Regarding claim 8: Popovici et al. disclose (i.e. figures 3 and 7) a converting device (i.e. 300), comprising:
a first transistor (i.e. Q1) coupled to a first node (i.e. N1);
a second transistor (i.e. Q2) coupled to a second node (i.e. N2); and
an input power source (i.e. Vin) configured to generate a primary current (i.e. Ip) that flows from the first node (i.e. N1) through a primary coil (i.e. 320) to the second node (i.e. N2),
wherein when the second transistor (i.e. Q2) is disconnected (i.e. Off), charge the second node (i.e. N2) through the first transistor (i.e. Q1) by the input power source (i.e. Vin) (i.e. ¶ 28-31 and 47-50).
Regarding claim 9: (i.e. figures 3 and 7) wherein: during a delayed time (i.e. time of DBBM at t2-t2’) when the second transistor (i.e. Q2, figure 7: signal ZVS2) is disconnected (i.e. Off), discharge the second node (i.e. N2) by the second transistor (i.e. Q2) to decrease a voltage (i.e. voltage at N2) of the second node (i.e. N2); and
when the voltage (i.e. voltage at N2) of the second node (i.e. N1) is adjusted to a first voltage level (i.e. voltage level provides at N2 when Q1 or Q2 is off), disconnect the second transistor (i.e. Q2 off) (i.e. ¶ 28-31 and 47-50).
Allowable Subject Matter
7. Claims 2-7 and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
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