DETAILED ACTION
Claims 1-21 are presented for examination.
This office action is in response to submission of application on 02-DEC-2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02-DEC-2024 and on 1-JULY-2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR-10-2024-0070787, filed on 30-MAY-2024.
Specification
The disclosure is objected to because of the following informalities:
In [0074], line 15, “CS1a to CS2d” should read “CS1a to CS1d” to properly refer to the cell strings connected to BL1.
In [0074], line 17, “CS1a to CS2d” should read “CS2a to CS2d” to properly refer to the cell strings connected to BL2.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7-9, 11-14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”).
Regarding claim 1: Kim teaches a memory device comprising:
A memory cell array including a first block ([0015], Kim teaches that a memory array with memory cells can include blocks.).
A control logic circuit configured to receive an erase command from an external controller and to control an erase operation on the first memory block in response to the erase command ([0011-0012], Kim teaches that a computing system may have a host device, which includes processors that can write or read data, as well as a memory system with a host interface which receives commands from the host device, and that the host device may include an upstream processor. Further, in [0015], Kim teaches an erase operation that can be performed on the memory array. The claimed control logic circuit is any kind of circuitry which can receive erase commands and controls erase operations. Therefore, the claimed limitation is taught by Kim.)
an open block duration timer configured to begin measuring a first open block duration time of the first memory block in response to block opening; and a memory circuit configured to store an open block duration table that stores the first open block duration time ([0022], Kim teaches a memory management mechanism that tracks the open duration for partially filled blocks, with one example embodiment being a block tracking list.)
when the first open block duration time exceeds a reference time ([0031-0036], Kim teaches a process where a memory system identifies when an open duration is less or not less than an open duration threshold for further operation, where in response to the open duration being not less than an open duration threshold, the memory system can program the block and/or close the block. Since, in [0013], Kim teaches that a memory system controller controls the overall operation of the memory system, including the memory array, the memory system performing that identification is interpreted to be the control logic determining and providing the information.)
while Kim teaches a separate array controller to the processor of the memory system controller, and that a timer starts upon opening a new block, Kim does not appear to explicitly disclose, an erase to program interval (EPI) timer configured to begin measuring a first EPI time of the first memory block in response to the erase command or when the first EPI time exceeds a reference time, the control logic circuit is further configured to provide EPI information to the external controller
However, Yu teaches an erase to program interval (EPI) timer configured to begin measuring a first EPI time of the first memory block in response to the erase command ([0055], Yu teaches a timer which determines as an EPI, the elapsed time since the most recent erase operation for the block.).
Yu further teaches the control logic circuit is further configured to provide EPI information to the external controller ([0032], Yu teaches a control logic element that controls operations of the memory device. Further, in [0094-0095] and in [0108], Yu teaches that the EPI information can be stored in the memory device, that a memory controller generates control information based on identified EPI, and further teaches an embodiment where the EPI detector and all timers are on the memory device. Furthermore, in [0104-0105], Yu teaches that the memory controller may determine the EPI of a block by obtaining the EPI detection result from an EPI detector as part of processing a write request. Therefore, although not explicitly taught within the same embodiment, an embodiment where all EPI information and EPI components are on the memory device, and the memory controller identifies the EPI information as part of processing requests, is an obvious combination. In such a case, the memory controller needs to generate control information using the EPI information, and would require the EPI information to be provided, which would come from the memory device side.)
Kim and Yu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim and Yu to achieve the result of a memory device with a control logic circuit that receives erase commands from an external controller, and controls erase operations in response to erase commands, and has a timer which measures an EPI time of a memory block in response to an erase, and where there is an EPI table that stores an EPI time, and when the EPI time exceeds a reference time, the EPI information is provided from the control logic circuit to the external controller.
One of ordinary skill in the art would have been motivated to make this modification in order to combine two physical arrangements which monitor the same problem of a degradation of charge/voltage for data programmed into the open blocks as a function of time as discussed in Kim [0021] and Yu [0033].
Regarding claim 2: The combination of Kim and Yu teaches all limitations of claim 1, from which claim 2 depends.
Kim/Yu further teaches the first memory block includes a plurality of memory cells, and each of the plurality of memory cells is a NAND flash memory cell ([0015], Kim teaches that the system uses NAND-based memory, where there are selected memory cells, which are included within memory blocks).
Regarding claim 4: The combination of Kim and Yu teaches all limitations of claim 1, from which claim 4 depends.
Kim/Yu further teaches when a command for the first memory block is not received within a specified time from a time the EPI information is provided to the external controller, the control logic circuit is further configured to perform a close operation on the first memory block ([0032-0036], Kim teaches that when an open duration is not less than the threshold, the memory system eventually may close the block after various checks, which would occur in all cases, including when a command for the first memory block is not received within a time after the EPI information was provided to an external controller, as described with respect to claim 1.)
Regarding claim 7: The combination of Kim and Yu teaches all limitations of claim 1, from which claim 7 depends.
Kim/Yu further teaches the control logic circuit is further configured to receive the erase command through a command/address channel ([0027-0028] and Fig. 1, Yu teaches a hardware embodiment where a memory controller controls a memory device, where write, read, and erase operations are controller by the memory controller by providing an address, a command, a control signal, and by exchanging data between the controller and the memory device, and in the figure, shows a combined CMD/ADDR line separate to the data and control lines.)
Considering the memory device and the functions of the invention of claim 1 as an improvement to memory devices, and the particular channel arrangement through which commands and data are received as a base memory device, one of ordinary skill in the art would have recognized that applying the improvement to the base memory device would have yielded the predictable result of a base memory device with the channel arrangement, which incorporates the additional functions and elements of claim 1.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu to achieve the result of the memory device of claim 1, which receives the erase command through a command/address channel.
Regarding claim 8: The combination of Kim and Yu teaches all limitations of claim 7, from which claim 8 depends.
Kim/Yu further teaches the control logic circuit is further configured to: receive a program command for the first memory block from the external controller through the command/address channel; receive data from the external controller through an input/output channel; and program the data in the first memory block in response to the program command, and wherein the command/address channel and the input/output channel are physically separated from each other (As described with respect to claim 7, Kim/Yu teaches an embodiment where write commands are sent from a controller to a memory device through a combined CMD/ADDR line that is separate from a DATA line. Further, in [0028], Yu teaches that the data that may be exchanged between the memory controller and memory device may be data to be written to the memory device, and that the memory controller would control the operation to write the data to the memory device.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 7.
Regarding claim 9: The combination of Kim and Yu teaches all limitations of claim 8, from which claim 9 depends.
Kim/Yu further teaches the control logic circuit is further configured to transmit the EPI information to the external controller through the command/address channel (As discussed with respect to claim 1, Yu teaches that control logic circuit is configured to transmit the EPI information to the external controller. In [0044], Yu teaches a general memory interface that provides physical connection between the memory controller and the memory device and facilitates communication between them, which allows the command/address/data to be exchanged between them. Taking into account the embodiment that the EPI information is transmitted from the memory device to the memory controller, and that signals and data are exchanged via particular physical interfaces, an embodiment where the EPI information is transmitted to the controller through a command/address channel is obvious.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 7.
Regarding claim 11: Kim teaches a storage device comprising:
A memory device including a first block ([0015], Kim teaches that a memory array with memory cells can include blocks.).
a controller configured to control the memory device ([0013], Kim teaches a memory system controller which controls the operation of the memory system, including for the array.)
perform an erase operation on the first memory block in response to an erase command from the controller ([0015], Kim teaches an erase operation that can be performed on the memory array. Since the controller controls such operations, the performing an erase in response to an erase command from a controller is taught.)
begin measuring a first open block duration time of the first memory block in response to block opening; ([0022], Kim teaches a memory management mechanism that tracks the open duration for partially filled blocks.)
when the first open block duration time exceeds a reference time… the controller is further configured to perform a program operation on the first memory block or a close operation on the first memory block in response to the EPI information ([0031-0036], Kim teaches a process where a memory system identifies when an open duration is less or not less than an open duration threshold for further operation, where in response to the open duration being not less than an open duration threshold, the memory system can program the block and/or close the block. In other words, the memory system identifies that the open block duration time exceeds the threshold, when it exceeds the threshold, for further performing a program operation or a close operation in response to the EPI information.)
while Kim teaches a separate array controller to the processor of the memory system controller, and that a timer starts upon opening a new block, Kim does not appear to explicitly disclose, begin measuring an erase to program interval (EPI) time of the first memory block in response to the erase command or transmit EPI information to the controller when the first EPI time exceeds a reference time
However, Yu teaches begin measuring an erase to program interval (EPI) time of the first memory block in response to the erase command ([0055], Yu teaches a timer which determines as an EPI, the elapsed time since the most recent erase operation for the block.).
Yu further teaches transmit EPI information to the controller when the first EPI time exceeds a reference time ([0032], Yu teaches a control logic element that controls operations of the memory device. Further, in [0094-0095] and in [0108], Yu teaches that the EPI information can be stored in the memory device, that a memory controller generates control information based on identified EPI, and further teaches an embodiment where the EPI detector and all timers are on the memory device. Furthermore, in [0104-0105], Yu teaches that the memory controller may determine the EPI of a block by obtaining the EPI detection result from an EPI detector as part of processing a write request. Therefore, although not explicitly taught within the same embodiment, an embodiment where all EPI information and EPI components are on the memory device, and the memory controller identifies the EPI information as part of processing requests, is an obvious combination. In such a case, the memory controller needs to generate control information using the EPI information, and would require the EPI information to be provided, which would come from the memory device side)
Kim and Yu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim and Yu to achieve the result of a memory device with a control logic circuit that receives erase commands from an external controller, and controls erase operations in response to erase commands, and has a timer which measures an EPI time of a memory block in response to an erase, and where there is an EPI table that stores an EPI time, and when the EPI time exceeds a reference time, the EPI information is provided from the control logic circuit to the external controller, and a program or close operation is performed.
One of ordinary skill in the art would have been motivated to make this modification in order to combine two physical arrangements which monitor the same problem of a degradation of charge/voltage for data programmed into the open blocks as a function of time as discussed in Kim [0021] and Yu [0033].
Regarding claim 12: The combination of Kim and Yu teaches all limitations of claim 11, from which claim 12 depends.
Kim/Yu further teaches the controller and the memory device communicate with each other through a command/address channel and an input/output channel ([0027-0028] and Fig. 1, Yu teaches a hardware embodiment where a memory controller controls a memory device, where write, read, and erase operations are controller by the memory controller by providing an address, a command, a control signal, and by exchanging data between the controller and the memory device, and in the figure, shows a combined CMD/ADDR line separate to the data and control lines.)
Considering the memory device and the functions of the invention of claim 11 as an improvement to storage devices, and the particular channel arrangement through which commands and data are received as a base storage device, one of ordinary skill in the art would have recognized that applying the improvement to the base storage device would have yielded the predictable result of a base storage device with the channel arrangement, which incorporates the additional functions and elements of claim 11.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu to achieve the result of the memory device of claim 11, which receives the erase command through a command/address channel.
Regarding claim 13: The combination of Kim and Yu teaches all limitations of claim 12, from which claim 13 depends.
Kim/Yu further teaches the controller is configured to transmit the erase command to the memory device through the command/address channel ([0027-0028] and Fig. 1, Yu teaches a hardware embodiment where a memory controller controls a memory device, where erase operations are controller by the memory controller by providing an address, a command, a control signal, and by exchanging data between the controller and the memory device, and in the figure, shows a combined CMD/ADDR line separate to the data and control lines.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 12.
Regarding claim 14: The combination of Kim and Yu teaches all limitations of claim 13, from which claim 14 depends.
Kim/Yu further teaches transmit a program command for the first memory block to the memory device through the command/address channel; and transmit data to be programmed in the first memory block to the memory device through the an input/output channel; and wherein the controller is further configured to program the data received through the input/output channel in the first memory block in response to the program command received through the command/address channel (As described with respect to claim 12, Kim/Yu teaches an embodiment where write commands are sent from a controller to a memory device through a combined CMD/ADDR line that is separate from a DATA line. Further, in [0028], Yu teaches that the data that may be exchanged between the memory controller and memory device may be data to be written to the memory device, and that the memory controller would control the operation to write the data to the memory device.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 12.
Regarding claim 19: Kim teaches an operation method of a storage device which includes a memory device and a controller, the method comprising: ([0013], Kim teaches a memory system with a controller and memory array, which performs the operations of the invention)
Transmitting, by the controller, an erase command for a first memory block to the memory device; performing, by the memory device, an erase operation on the first memory block in response to the erase command ([0013-0019], Kim teaches that the controllers control the overall operation of the memory array, and that the controller may handle the transport of data to the memory array, and that the memory array contains components which are used for accessing data on the array, and that one of the operations that can be performed is an erase operation. Therefore, Kim teaches that, to perform an erase operation, the controller transmits erase instructions to the memory device, and the erase operation is performed in response to it.)
Starting, by the memory device, to measure a open block duration time of the first memory block; ([0022], Kim teaches a memory management mechanism that tracks the open duration for partially filled blocks, with one example embodiment being a block tracking list.)
transmitting, by the controller, a program command and data to the memory device; programming, by the memory device, the data in the first memory block in response to the program command; ([0016], Kim teaches components of the array which are used to access or program data to the memory array.)
EPI information… when the first open block duration time exceeds a reference threshold; and performing, by the controller, a program operation or a close operation on the first memory block in response to the EPI information ([0031-0036], Kim teaches a process where a memory system identifies when an open duration is less or not less than an open duration threshold for further operation, where in response to the open duration being not less than an open duration threshold, the memory system can program the block and/or close the block. In other words, the memory system identifies that the open block duration time exceeds the threshold, when it exceeds the threshold, for further performing a program or a close operation in response to the infomation.)
while Kim teaches a separate array controller to the processor of the memory system controller, and that a timer starts upon opening a new block, Kim does not appear to explicitly disclose, starting, by the memory device, to measure a first EPI time of the first memory block; transmitting, by the memory device, EPI information to the controller when the first EPI time exceeds a reference threshold;
However, Yu teaches starting, by the memory device, to measure a first EPI time of the first memory block; ([0055], Yu teaches a timer which determines as an EPI, the elapsed time since the most recent erase operation for the block.).
Yu further teaches transmitting, by the memory device, EPI information to the controller when the first EPI time exceeds a reference threshold; ([0032], Yu teaches a control logic element that controls operations of the memory device. Further, in [0094-0095] and in [0108], Yu teaches that the EPI information can be stored in the memory device, that a memory controller generates control information based on identified EPI, and further teaches an embodiment where the EPI detector and all timers are on the memory device. Furthermore, in [0104-0105], Yu teaches that the memory controller may determine the EPI of a block by obtaining the EPI detection result from an EPI detector as part of processing a write request. Therefore, although not explicitly taught within the same embodiment, an embodiment where all EPI information and EPI components are on the memory device, and the memory controller identifies the EPI information as part of processing requests, is an obvious combination. In such a case, the memory controller needs to generate control information using the EPI information, and would require the EPI information to be provided, which would come from the memory device side)
Kim and Yu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim and Yu to achieve the result of a memory device with a control logic circuit that receives erase commands from an external controller, and controls erase operations in response to erase commands, and has a timer which measures an EPI time of a memory block in response to an erase, and where there is an EPI table that stores an EPI time, and when the EPI time exceeds a reference time, the EPI information is provided from the control logic circuit to the external controller.
One of ordinary skill in the art would have been motivated to make this modification in order to combine two physical arrangements which monitor the same problem of a degradation of charge/voltage for data programmed into the open blocks as a function of time as discussed in Kim [0021] and Yu [0033].
Regarding claim 20: The combination of Kim and Yu teaches all limitations of claim 19, from which claim 20 depends.
Kim/Yu further teaches the controller transmits the erase command and the program command to the memory device through a command/address channel and transmits the data to the memory device through an input/output channel, and ([0027-0028] and Fig. 1, Yu teaches a hardware embodiment where a memory controller controls a memory device, where write, read, and erase operations are controller by the memory controller by providing an address, a command, a control signal, and by exchanging data between the controller and the memory device, and in the figure, shows a combined CMD/ADDR line separate to the data and control lines.)
wherein the memory device transmits the EPI information to the controller through the command/address channel (As discussed with respect to claim 19, Yu teaches that control logic circuit is configured to transmit the EPI information to the external controller. In [0044], Yu teaches a general memory interface that provides physical connection between the memory controller and the memory device and facilitates communication between them, which allows the command/address/data to be exchanged between them. Taking into account the embodiment that the EPI information is transmitted from the memory device to the memory controller, and that signals and data are exchanged via particular physical interfaces, an embodiment where the EPI information is transmitted to the controller through a command/address channel is obvious.)
Considering the storage device and the steps of the method of claim 19 as an improvement to storage devices, and the particular channel arrangement through which commands and data are received as a base storage device, one of ordinary skill in the art would have recognized that applying the improvement to the base storage device would have yielded the predictable result of a base storage device with the particular channel and command/EPI information transmission arrangement, which incorporates the additional functions and elements of claim 19.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu to achieve the result of the memory device of claim 19, which receives the erase command through a command/address channel.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
Masuo et al., U.S. Patent No. 9361201 (hereinafter “Masuo).
Regarding claim 3: The combination of Kim and Yu teaches all limitations of claim 1, from which claim 3 depends.
Kim/Yu teaches completion of programming a last word line of the first memory block ([0033], Kim teaches that the memory system can determine that a targeted block is full, then closes the memory block and moves the write pointer to a new block. While not explicit, determining that a targeted block is full means that the last word lines of a first memory block are programmed.)
Kim/Yu does not appear to explicitly disclose upon completion of programming a last word line of the first memory block, the EPI timer is further configured to clear the first EPI time from the EPI table
However, Masuo teaches upon completion of programming a last word line of the first memory block, the EPI timer is further configured to clear the first EPI time from the EPI table ([Col. 11, lines 38-42, Masuo teaches that erase time information may only need to be stored for blocks after erasure that are in the writing state.).
Kim/Yu and Masuo are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Masuo to achieve the combined result of the memory device of claim 1, which closes a block upon completion, thereby considering the block not in a writing state, to also no longer store the erase time information for the block upon the block not being in a writing state.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce the memory capacity needed for storing the block management tables as discussed in Masuo Col. 11 lines 43-44.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
HOSOTANI et al., U.S. Pub. No. 20200286828 (hereinafter “Hosotani”)
Regarding claim 5: The combination of Kim and Yu teaches all limitations of claim 4, from which claim 5 depends.
Kim/Yu does not appear to explicitly disclose The control logic circuit is further configured to transmit close information, indicating the close operation on the first memory block has been performed, to the external controller.
However, Hosotani teaches The control logic circuit is further configured to transmit information, indicating the operation on the first memory block has been performed, to the external controller. ([0032-0035], Hosotani teaches an internal circuitry of a semiconductor memory device, in which the internal circuitry includes a status register which temporarily holds status information of, for example, a write operation, a read operation, and an erase operation, and notifies an external controller whenever the operation is completed).
Kim/Yu and Hosotani are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Hosotani to achieve the combined result of the device of claim 3, where when the block is closed, an external controller is notified whenever an operation is complete.
One of ordinary skill in the art would have been motivated to make this modification as part of a normal operation cycle of a system with an input/output circuit which controls signals between an external controller and a storage’s internal logic controller, as discussed in Hosotani [0033].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
Ahn, U.S. Pub. No. 20060044875 (hereinafter “Ahn”).
Regarding claim 6: The combination of Kim and Yu teaches all limitations of claim 1, from which claim 6 depends.
Kim/Yu further teaches receive a first command from the external controller; and transmit the EPI information to the external controller in response to the first command, and; (As discussed with respect to claim 1, Yu teaches the structure for which, in response to a command from an external controller, EPI information is transmitted from the control logic circuit to the external controller.)
Kim/Yu does not appear to explicitly disclose wherein the first command is a status read command, a get feature command, or a vendor command.
However, Ahn teaches wherein the first command is a status read command, a get feature command, or a vendor command. ([0082], Ahn teaches a READ STATUS command, wherein the result of a state verification of blocks is output in response to the command.).
Kim/Yu and Ahn are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Ahn to achieve the combined result of the device of claim 1, where the circuit can handle READ STATUS commands and output the associated EPI status of the blocks in response to them.
One of ordinary skill in the art would have been motivated to make this modification as an obvious possible implementation of the providing the EPI information to the external controller found in claim 1.
Claims 10, 15, 21 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
Lee, U.S. Patent No. 9740657 (hereinafter “Lee”).
Regarding claim 10: The combination of Kim and Yu teaches all limitations of claim 9, from which claim 10 depends.
Kim/Yu does not appear to explicitly disclose while the data are being transmitted from the external controller to the memory device through the input/output channel, the control logic circuit transmits the EPI information to the external controller through the command/address channel.
However, Lee teaches simultaneously processing memory access requests through different channels (Col. 2 lines 1-14, Lee teaches that the various ports of a memory system can be simultaneously active to process multiple memory access requests).
Kim/Yu and Lee are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Lee to achieve the combined result of the system which transmits data to be programmed from an external controller through one input/output channel, and needs to transmit the EPI information to an external controller via a separate command/address channel, to do so simultaneously.
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 7.
Regarding claim 15: The combination of Kim and Yu teaches all limitations of claim 14, from which claim 15 depends.
Kim/Yu does not appear to explicitly disclose while the data are being received through the input/output channel, the memory device is further configured to provide the EPI information to the controller through the command/address channel.
However, Lee teaches simultaneously processing memory access requests through different channels (Col. 2 lines 1-14, Lee teaches that the various ports of a memory system can be simultaneously active to process multiple memory access requests).
Kim/Yu and Lee are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Lee to achieve the combined result of the system which transmits data to be programmed from an external controller through one input/output channel, and needs to transmit the EPI information to an external controller via a separate command/address channel (as discussed with respect to claim 11), to do so simultaneously.
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 12.
Regarding claim 21: Kim teaches a storage device comprising:
A memory device including a first memory block, and configured to manage a first open block duration time of the first memory block; and a controller configured to communicate with the memory device ([0015-0017], Kim teaches a memory device having memory blocks, and a controller which communicates with it. [0022], Kim teaches a memory management mechanism that tracks the open duration for partially filled blocks, with one example embodiment being a block tracking list.)
Transmitting, by the controller, an erase command for a first memory block to the memory device; performing, by the memory device, an erase operation on the first memory block in response to the erase command ([0013-0019], Kim teaches that the controllers control the overall operation of the memory array, and that the controller may handle the transport of data to the memory array, and that the memory array contains components which are used for accessing data on the array, and that one of the operations that can be performed is an erase operation. Therefore, Kim teaches that, to perform an erase operation, the controller transmits erase instructions to the memory device, and the erase operation is performed in response to it.)
Receive a program command…; and program data received… in the first memory block in response to the program command ([0013-0019], Kim teaches that the controller controls the overall operation of the memory array, including to send data to the memory array, and that there are components on the memory array for performing program operations, in which data is programmed into the memory cells)
when the first open block duration time exceeds a threshold; ([0031-0036], Kim teaches a process where a memory system identifies when an open duration is less or not less than an open duration threshold for further operation, where in response to the open duration being not less than an open duration threshold, the memory system can program the block and/or close the block. In other words, the memory system identifies that the open block duration time exceeds the threshold, when it exceeds the threshold, for further operation.)
while Kim teaches a separate array controller to the processor of the memory system controller, and that a timer starts upon opening a new block, Kim does not appear to explicitly disclose, manage a first erase to program interval (EPI) time of the first memory block; or when the first EPI time exceeds a threshold, the memory device is further configured to transmit EPI information to the controller through the command/address channel while the data are being received through the input/output channel.
However, Yu teaches manage a first erase to program interval (EPI) time of the first memory block; ([0055], Yu teaches a timer which determines as an EPI, the elapsed time since the most recent erase operation for the block.).
Yu further teaches when the first EPI time exceeds a threshold, the memory device is further configured to transmit EPI information to the controller through the command/address channel… the data are being received through the input/output channel. ([0032], Yu teaches a control logic element that controls operations of the memory device. Further, in [0094-0095] and in [0108], Yu teaches that the EPI information can be stored in the memory device, that a memory controller generates control information based on identified EPI, and further teaches an embodiment where the EPI detector and all timers are on the memory device. Furthermore, in [0104-0105], Yu teaches that the memory controller may determine the EPI of a block by obtaining the EPI detection result from an EPI detector as part of processing a write request. Therefore, although not explicitly taught within the same embodiment, an embodiment where all EPI information and EPI components are on the memory device, and the memory controller identifies the EPI information as part of processing requests, is an obvious combination. In such a case, the memory controller needs to generate control information using the EPI information, and would require the EPI information to be provided, which would come from the memory device side. Furthermore, in [0028] and [0044] and in Fig. 1, Yu teaches a particular hardware embodiment in which there are separate lines for DATA and for CMD/ADDR, which facilitate communication between the controller and the memory device. With a particular set of lines that provide communication between the memory controller and memory device, and knowing that the EPI information is sent from the memory device to the memory controller, an embodiment where the EPI information is transmitted through the command/address line is obvious.)
Kim and Yu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim and Yu to achieve the result of a memory device with a control logic circuit that receives erase commands from an external controller, and controls erase operations in response to erase commands, and has a timer which measures an EPI time of a memory block in response to an erase, and where there is an EPI table that stores an EPI time, and when the EPI time exceeds a reference time, the EPI information is provided from the control logic circuit to the external controller.
One of ordinary skill in the art would have been motivated to make this modification in order to combine two physical arrangements which monitor the same problem of a degradation of charge/voltage for data programmed into the open blocks as a function of time as discussed in Kim [0021] and Yu [0033].
Kim/Yu does not appear to explicitly disclose the memory device is further configured to transmit EPI information to the controller through the command/address channel while the data are being received through the input/output channel.
However, Lee teaches simultaneously processing memory access requests through different channels (Col. 2 lines 1-14, Lee teaches that the various ports of a memory system can be simultaneously active to process multiple memory access requests).
Kim/Yu and Lee are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu and Lee to achieve the combined result of the system which transmits data to be programmed from an external controller through one input/output channel, and needs to transmit the EPI information to an external controller via a separate command/address channel, to do so simultaneously.
One of ordinary skill in the art would have been motivated to make this modification as part of a possible physical arrangement of components to perform the steps of the invention.
Claims 16, 17 are rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
Lee, U.S. Patent No. 9740657 (hereinafter “Lee”) further in view of
WU et al., U.S. Pub. No. 20230195658 (hereinafter “Wu”).
Regarding claim 16: The combination of Kim, Yu, and Lee teaches all limitations of claim 15, from which claim 16 depends.
Kim/Yu/Lee further teaches while the data are being received through the input/output channel, the controller provides a first command/address packet including a first command to the memory device through the command/address channel. (As discussed with respect to claim 15, Lee teaches the simultaneous transfers through the different channels. Further, as discussed with respect to claim 14, Yu teaches the data being transmitted through an input/output channel, and command information through the command/address channel. Although not explicit, the command and address information being sent taught in Yu [0041] is interpreted to be a command/address packet.)
Kim/Yu/Lee further teaches wherein the memory device provides the EPI information to the controller through the command/address channel in response to the first command included in the first command/address packet (As discussed with respect to claim 15, Lee teaches the simultaneous transfers through the different channels. Further, as discussed with respect to claim 14, Yu teaches the data being transmitted through an input/output channel, and command information through the command/address channel. Further, as discussed with respect to claim 11, EPI information is transmitted between the controller and device, in response to a command.)
Kim/Yu/Lee does not appear to explicitly disclose wherein the first command/address packet includes a first header and a first body, and wherein the first header indicates a command input, and the first body includes information about the first command.
However, Wu teaches memory request packets include a header and a body, wherein the header indicates a command input, and the body includes information about the request ([0036], Wu teaches that memory requests may include a header and a body, where the header may include address information indicating a logical address for the memory request, which is interpreted as the claimed first command/address packet including a first header which indicates a command input. Wu further teaches the body, which includes information such as the commands for a memory request and data associated with the request, which is interpreted as the claimed first body which includes information about the first command).
Kim/Yu/Lee and Wu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu/Lee and Wu to achieve the combined result of the system which transmits data to be programmed from an external controller through one input/output channel, and needs to transmit the EPI information to an external controller via a separate command/address channel (as discussed with respect to claim 11), to do so simultaneously, wherein the command/address packets sent for a first command include a first header with first command input, and a first body with information about the first command.
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 12.
Regarding claim 17: The combination of Kim, Yu, and Lee teaches all limitations of claim 15, from which claim 17 depends.
Kim/Yu/Lee further teaches while the data are being received through the input/output channel… while the data are being received through the input/output channel, the device provides the EPI information through the command/address channel in response to the second command (As discussed with respect to claim 15, Lee teaches the simultaneous transfers through the different channels. Further, as discussed with respect to claim 14, Yu teaches the data being transmitted through an input/output channel, and command information through the command/address channel. Further, with respect to claim 11, Kim/Yu teaches the EPI being sent through the command/address channel in response to commands.)
Kim/Yu/Lee does not appear to explicitly disclose the controller transmits a second header to the memory device through the command/address channel or other action in response to the second header
However, Wu teaches memory request packets include a header and a body, wherein the header indicates a command input, and the body includes information about the request ([0036], Wu teaches that memory requests may include a header and a body, where the header may include address information indicating a logical address for the memory request. Furthermore, in [0041], Yu teaches that the command and address information is transmitted via the command/address).
Kim/Yu/Lee and Wu are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu/Lee and Wu to achieve the combined result of the system which transmits data to be programmed from an external controller through one input/output channel, and needs to transmit the EPI information to an external controller via a separate command/address channel (as discussed with respect to claim 11), to do so simultaneously, wherein the EPI information is sent in response to a command that includes a second header.
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 12.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over
Kim, U.S. Pub. No. 20240020037 (hereinafter “Kim”), in view of
Yu et al., U.S. Pub. No. 20200381068 (hereinafter “Yu”) further in view of
Lee, U.S. Patent No. 9740657 (hereinafter “Lee”) further in view of
WU et al., U.S. Pub. No. 20230195658 (hereinafter “Wu”) further in view of
Wu, U.S. Pub. No. 20230393931 (hereinafter “Wu 931”)
Regarding claim 18: The combination of Kim, Yu, Lee, and Wu teaches all limitations of claim 17, from which claim 18 depends.
While Yu teaches a CTRL line that controls aspects of how a program is performed, Kim/Yu/Lee/Wu does not appear to explicitly disclose the command/address channel includes a 0-th command/address signal line and a first command/address line, wherein the memory device is configured to: identify the second header received through the 0-th and first command/address signal lines based on a command/address clock; output a toggle signal through the 0-th command/address signal line, based on the command/address clock, in response to the second header; and output a second body including the EPI information to the controller through the first command/address signal line in synchronization with the toggle signal output through the 0-th command/address line.
However, Wu 931 teaches multiple lines used to transmit parts of command/address signals, based on a clock which triggers the sending of clock signals ([0021-0023], Wu 931 teaches a memory device in which the components that transmit a signal to the memory device are data lines and control lines, where the control lines may send clock signals or interrupt signals. The data lines have a number of lines that transmit signals representing the bits of commands, addresses, or data according to the clock signal. Furthermore, in [0032-0036], Wu 931 teaches a particular clock signal that corresponds to clock cycles, in which the various bits of a command/address/data item are transmitted according to the clock cycles in the clock signal. While not explicitly taught in the same way as the claimed invention, the clock signal which corresponds to clock cycles, which are sent through a new line, in view of claim 17, are interpreted as rendering obvious the claimed identifying the headers and outputting a toggle signal based on the clock, and outputting a second body in synchronization with the toggle signal output).
Kim/Yu/Lee/Wu and Wu 931 are analogous art because they are from the same field of endeavor, memory device management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Kim/Yu/Lee/Wu and Wu 931 to achieve the combined result of the system of claim 17 which transmits data and commands between a storage device via respective channels, to further include an additional 0-th command/address signal line through which a signal is transmitted, which causes the other second header of Kim/Yu/Lee/Wu to be sent and received (identified) based on a command/address clock, which outputs a toggle signal through the new line based on the clock, and would be in response to a command being received (which is when the second header is received), and through which a second body including the EPI information is output in synchronization with the toggle signal output, which is based on a clock.
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jang et al., U.S. Pub. No. 20210248069, teaches that an open block time can be interpreted as an erase to program interval.
MUTHIAH et al., U.S. Pub. No. 20230409236, teaches that when a block remains open for too long, the system can close the block or prioritize commands in a queue to target the block in order to fill it.
Moon et al., U.S. Patent No. 9798657, teaches a dummy closing operation that occurs at a reference time since when the block was erased.
Yu et al., U.S. Pub. No. 20210065828 teaches specific physical channels through which CMD/ADDR information is transmitted, and separate physical channels through which DATA is transmitted.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133