CTNF 18/965,499 CTNF 82450 DETAILED ACTION The current Office Action is in response to the papers submitted 12/03/2024. Claims 2 - 21 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 7, 13 – 14, and 20 - 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation "the other of the plurality of memory devices" in line 3. There is no previous mention of other of the plurality of memory devices in the claim or base claim. There is insufficient antecedent basis for this limitation in the claim. For examination the limitation will be treated as referring to memory devices that are not the target or the mirror memory device. Claim 13 recites the limitation of “a plurality of segments that are received during a plurality of clock cycles, respectively” in lines 2 – 3. It is unclear how the segments and the clock cycles are related. The “respectively” limitation could mean each of the plurality of segments are received in one of a plurality of clock cycles or each segments is received during a plurality of clock cycles. This makes the limitation and claim indefinite. Claim 14 contains similar language as claim 7 and is rejected for similar reasoning as claim 7. Claim 20 contains similar language as claim 13 and is rejected for similar reasoning as claim 13. Claim 21 contains similar language as claim 7 and is rejected for similar reasoning as claim 7. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 – 4 and 7 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yu et al. (Pub. No.: US 2011/0302358) referred to as Yu . Regarding claim 2 , Yu teaches a first controller [104, Fig 6; The host is a controller that controls item 100] including a first data output [Fig 6; The output of 104 connected to 50] ; a second controller [100, Fig 6; The switch is a controller of memory 10] including a second data output [Fig 6; The output connected to 10] , and a first data input that is connected to the first data output [Fig 6; The input connection of 50 is connected to the output of 104] ; and a plurality of memory devices [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , wherein the second controller [100, Fig 6] is configured to: receive, at the first data input [Fig 6; The input connection of 50 is connected to the output of 104] , a write command [Paragraphs 0060 and 0068; The operations performed include write operations] , an address, and storage data [58, Fig 6; Paragraph 0074; Data, address, and command information are all sent from the first controller 104 and stored in buffer 58] that are output from the first data output [Fig 6; The output of 104 connected to 50] , when a first communication path is enabled between the first controller [104, Fig 6] and the second controller [100, Fig 6; Sending data from 104 to 50 in 100 shows a communication path was enabled between 104 and 100] ; determine, based on the received address, a target memory device of a write operation in accordance with the write command [Paragraph 0073; Data, commands, and addresses are stored in a buffer and used, along with mapping table 48, to determine a target location based on the type of RAID implemented in controller 100] , among the plurality of memory devices [110, Figs 4] ; determine a mirror memory device corresponding to the determined target memory device, among the plurality of memory devices [110, Figs 4; Paragraph 0073; Mirror is performed which includes determining a mirror memory device to store a mirror copy of data] ; enable a second communication path between the second controller [100, Fig 6] and the target memory device and a third communication path between the second controller [100, Fig 6] and the mirror memory device [Paragraph 0073; Implementing a RAID that uses mirror shows a second communication path is enabled between a target memory device 110 in 10 and the second controller 100 to store first version of data. The mirror RAID implementation would also include a third communication path that is enabled between a mirror memory device 110 in 10 and the second controller 100 to store the mirror copy of the first version of data] ; and transmit the write command, at least part of the address, and the storage data to the target memory device via the enabled second communication path and to the mirror memory device via the enabled third communication path [Paragraph 0073; A RAID using mirroring would transfer the write command, data, and address information in the buffer to the memory devices 110 accordingly along the communication paths to each memory device based on the mirroring algorithm used] . Regarding claim 3 , Yu teaches the second controller [100, Fig 6] further includes a buffer [58, Fig 6] , the second controller [100, Fig 6] is further configured to store the received write command, the received address, and the received storage data into the buffer [58, Fig 6; Paragraph 0073; Commands, data, and addresses are stored in the buffer] , and the write command, the at least part of the address, and the storage data that are transmitted are output from the buffer [58, Fig 6; Paragraph 0073; The data, commands, and addresses are sent from the first controller 104 to the second controller 100 and stored in the buffer. The buffered information is used to perform the RAID operations from the first controller] . Regarding claim 4 , Yu teaches the second controller [100, Fig 6] is configured to maintain information indicating correspondence of one of the plurality of memory devices and a mirror memory device thereof, and determine the mirror memory device corresponding to the determined target memory device with reference to the information [48, 52 and 54; Items 48, 52, and 54 together contain the information used to implement mirroring between two memory locations] . Regarding claim 7 , Yu teaches when the second and third communication paths are enabled, no communication path is enabled between the second controller and the other of the plurality of memory devices than the target memory device and the mirror memory device [Paragraph 0073; Implementing a mirror RAID algorithm only enables the communication paths between the storage locations and storage the data is sent along] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 5 - 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Pub. No.: US 2011/0302358) referred to as Yu as applied to claim 2 above, and further in view of Lee et al. (Pub. No.: US 2013/0086309) referred to as Lee . Regarding claim 5 , Yu teaches a first controller [104, Fig 6; The host is a controller that controls item 100] including a first data output [Fig 6; The output of 104 connected to 50] ; a second controller [100, Fig 6; The switch is a controller of memory 10] including a second data output [Fig 6; The output connected to 10] , and a first data input that is connected to the first data output [Fig 6; The input connection of 50 is connected to the output of 104] ; and a plurality of memory devices [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , wherein the second controller [100, Fig 6] is configured to: receive, at the first data input [Fig 6; The input connection of 50 is connected to the output of 104] , a write command, an address, and storage data [58, Fig 6; Paragraph 0074; Data, address, and command information are all sent from the first controller 104 and stored in buffer 58] that are output from the first data output [Fig 6; The output of 104 connected to 50] , when a first communication path is enabled between the first controller [104, Fig 6] and the second controller [100, Fig 6; Sending data from 104 to 50 in 100 shows a communication path was enabled between 104 and 100] . However, Yu may not specifically disclose the limitation(s) of the first controller further includes a first enable output, the second controller further includes a first enable input that is connected to the first enable output, and the first communication path is enabled in accordance with an enable signal transmitted from the first enable output to the first enable input. Lee discloses first controller further includes a first enable output, the second controller further includes a first enable input that is connected to the first enable output, and the first communication path is enabled in accordance with an enable signal transmitted from the first enable output to the first enable input [710, Fig 7; Paragraphs 0103 and 0105; Control enable signals are sent and received between devices to allow devices to communicate showing the use of enable inputs and enable outputs to send and receive the control enable signals] . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee in Yu, because the enable signal allows for communication paths between devices to be enabled or not allowing control of where data is sent based on which data paths are enabled [Paragraph 0105] . Regarding claim 6 , Yu teaches the second controller [100, Fig 6] further includes a plurality of second outputs [Figs 5A and 6; Each SCFD 10 connected to the second controller 100 would be connected using a second output of the second controller 100] , each of the plurality of memory device [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , enable a second communication path between the second controller [100, Fig 6] and the target memory device and a third communication path between the second controller [100, Fig 6] and the mirror memory device [Paragraph 0073; Controlling the stripping and mirroring includes enabling proper communication paths based on the type of stripping and mirroring performed] . Lee discloses enabling communication paths between devices using enabling signals sent from an enable output of one device and received at an enable input of another device to allow communication between the devices [710, Fig 7; Paragraphs 0103 and 0105] . 07-21-aia AIA Claim (s) 8 – 10, 13 – 17, and 20 - 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Pub. No.: US 2011/0302358) referred to as Yu in view of Yanai et al. (Pub. No.: US 2006/0005074) referred to as Yanai . Regarding claims 8 , Yu teaches a first controller [104, Fig 6; The host is a controller that controls item 100] including a first data output [Fig 6; The output of 104 connected to 50] ; a second controller [100, Fig 6; The switch is a controller of memory 10] including a second data output [Fig 6; The output connected to 10] , and a first data input that is connected to the first data output [Fig 6; The input connection of 50 is connected to the output of 104] ; and a plurality of memory devices [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , wherein the second controller [100, Fig 6] is configured to: receive, at the first data input [Fig 6; The input connection of 50 is connected to the output of 104] , a read command [Paragraphs 0055 and 0061; The operations performed include read operations] , an address, and storage data [58, Fig 6; Paragraph 0074; Data, address, and command information are all sent from the first controller 104 and stored in buffer 58] that are output from the first data output [Fig 6; The output of 104 connected to 50] , when a first communication path is enabled between the first controller [104, Fig 6] and the second controller [100, Fig 6; Sending data from 104 to 50 in 100 shows a communication path was enabled between 104 and 100] ; determine whether or not mirroring is designated [Paragraph 0073; Controller 52 determines if mirroring or not is designated based on the desired type of RAID used since not all RAID implementations use mirroring] ; determine, as a target memory device of a read operation in accordance with the read command, one of the plurality of memory devices that is designated by the address when the mirroring is not designated or a mirror memory device corresponding to the one of the plurality of memory devices when the mirroring is designated [Paragraphs 0055, 0061, and 0073; The type of RAID implemented dictates the target of a read operation when mirroring is implemented or not] ; enable a second communication path between the second controller [100, Fig 6] and the target memory device [Paragraphs 0055, 0061, and 0073; Based on the RAID that is implemented a read operation causes a specific data path to be enabled between specific memory devices and the second controller to retrieve the requested data] ; and transmit the read command and at least part of the address to the target memory device via the enabled second communication path [Paragraphs 0055, 0061, and 0073; Implementing the read causes the read command and address information to be transmitted along the communication path to perform the read and retrieve the desired data] . However, Yu may not specifically disclose the limitation(s) of a controller determining whether or not mirroring is designated based on the received address. Yanai discloses a controller [16, Fig 1] determining whether or not mirroring is designated based on the received address [402, Fig 7; Paragraphs 0121 – 0123; A YES outcome in step 402 is a determination that mirroring is not designated based on the address of the read command being directed to a local volume that is not mirrored] . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yanai in Yu, because it reduces storage capacity requirements by allowing data to be stored in a system that is not mirrored while other data is mirrored. Claim 15 is a method corresponding to claim 8 and is rejected using the same prior art and reasoning as claim 8. Yu teaches the method [Figs 2 – 3C and 7] . Regarding claims 9 and 16 , Yu teaches the second controller [100, Fig 6] further includes a buffer [58, Fig 6] , the second controller [100, Fig 6] is further configured to store the received write command and the received address into the buffer [58, Fig 6; Paragraphs 0055, 0061, and 0073; Commands, data, and addresses are stored in the buffer] , and the read command [Paragraphs 0055 and 0061] and the at least part of the address that are transmitted are output from the buffer [58, Fig 6; Paragraphs 0055, 0061, and 0073; The data, commands, and addresses are sent from the first controller 104 to the second controller 100 and stored in the buffer. The buffered information is used to perform the RAID operations from the first controller] . Regarding claims 10 and 17 , Yu teaches Yu teaches the second controller [100, Fig 6] is configured to maintain information indicating correspondence of one of the plurality of memory devices and a mirror memory device thereof, and determine the mirror memory device corresponding to the one of the plurality of memory devices that is designated by the address, with reference to the information [48, 52 and 54; Items 48, 52, and 54 together contain the information used to implement mirroring between two memory locations] . Regarding claims 13 and 20 , Yu teaches wherein the address received from the first data output [Fig 6; The output of 104 connected to 50] includes a plurality of segments that are received during a plurality of clock cycles, respectively [Paragraphs 0055 and 0061; Each bit or byte of an address is a segment and the address segments are received during the clock cycles between the start of the read access and the end of the read access] , and Yanai discloses a leading one of the segments included in the received address indicates whether or not the mirroring is designated [402 and 408, Fig 7; Paragraphs 0121 – 0123; The address segments, including a leading segment, indicate if mirroring is designated or not] . Regarding claims 14 and 21 , Yu teaches when the second communication path is enabled, no communication path is enabled between the second controller and the other of the plurality of memory devices than the target memory device. [Paragraph 0073; Implementing a mirror RAID algorithm only enables the communication paths between the storage locations and storage the data is sent along] . 07-22-aia AIA Claim (s) 11 – 12 and 18 - 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Pub. No.: US 2011/0302358) referred to as Yu in view of Yanai et al. (Pub. No.: US 2006/0005074) referred to as Yanai as applied to claim s 8 and 15 above, and further in view of Lee et al. (Pub. No.: US 2013/0086309) referred to as Lee . Regarding claims 11 and 18 , Yu teaches a first controller [104, Fig 6; The host is a controller that controls item 100] including a first data output [Fig 6; The output of 104 connected to 50] ; a second controller [100, Fig 6; The switch is a controller of memory 10] including a second data output [Fig 6; The output connected to 10] , and a first data input that is connected to the first data output [Fig 6; The input connection of 50 is connected to the output of 104] ; and a plurality of memory devices [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , wherein the second controller [100, Fig 6] is configured to: receive, at the first data input [Fig 6; The input connection of 50 is connected to the output of 104] , a write command, an address, and storage data [58, Fig 6; Paragraph 0074; Data, address, and command information are all sent from the first controller 104 and stored in buffer 58] that are output from the first data output [Fig 6; The output of 104 connected to 50] , when a first communication path is enabled between the first controller [104, Fig 6] and the second controller [100, Fig 6; Sending data from 104 to 50 in 100 shows a communication path was enabled between 104 and 100] . However, Yu in view of Yanai may not specifically disclose the limitation(s) of the first controller further includes a first enable output, the second controller further includes a first enable input that is connected to the first enable output, and the first communication path is enabled in accordance with an enable signal transmitted from the first enable output to the first enable input. Lee discloses first controller further includes a first enable output, the second controller further includes a first enable input that is connected to the first enable output, and the first communication path is enabled in accordance with an enable signal transmitted from the first enable output to the first enable input [710, Fig 7; Paragraphs 0103 and 0105; Control enable signals are sent and received between devices to allow devices to communicate showing the use of enable inputs and enable outputs to send and receive the control enable signals] . Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee in Yu in view of Yanai, because the enable signal allows for communication paths between devices to be enabled or not allowing control of where data is sent based on which data paths are enabled [Paragraph 0105] . Regarding claims 12 and 19 , Yu teaches the second controller [100, Fig 6] further includes a plurality of second outputs [Figs 5A and 6; Each SCFD 10 connected to the second controller 100 would be connected using a second output of the second controller 100] , each of the plurality of memory device [110, Figs 4; The flash memory in a SCFD 10 is a memory device] , each of which includes a second data input that is connected to the second data output [10 and 110, Fig 4; 10 and 100, Fig 6; An SCFD 10 contains multiple memory devices 110 with an input that is connected to an output of switch 100] , enable a second communication path between the second controller [100, Fig 6] and the target memory device [Paragraph 0073; Controlling the stripping and mirroring includes enabling proper communication paths based on the type of stripping and mirroring performed] . Lee discloses enabling communication paths between devices using enabling signals sent from an enable output of one device and received at an enable input of another device to allow communication between the devices [710, Fig 7; Paragraphs 0103 and 0105] . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Christopher D Birkhimer/Primary Examiner, Art Unit 2138 Application/Control Number: 18/965,499 Page 2 Art Unit: 2138 Application/Control Number: 18/965,499 Page 3 Art Unit: 2138 Application/Control Number: 18/965,499 Page 4 Art Unit: 2138 Application/Control Number: 18/965,499 Page 5 Art Unit: 2138 Application/Control Number: 18/965,499 Page 6 Art Unit: 2138 Application/Control Number: 18/965,499 Page 7 Art Unit: 2138 Application/Control Number: 18/965,499 Page 8 Art Unit: 2138 Application/Control Number: 18/965,499 Page 9 Art Unit: 2138 Application/Control Number: 18/965,499 Page 10 Art Unit: 2138 Application/Control Number: 18/965,499 Page 11 Art Unit: 2138 Application/Control Number: 18/965,499 Page 12 Art Unit: 2138 Application/Control Number: 18/965,499 Page 13 Art Unit: 2138 Application/Control Number: 18/965,499 Page 14 Art Unit: 2138 Application/Control Number: 18/965,499 Page 15 Art Unit: 2138 Application/Control Number: 18/965,499 Page 16 Art Unit: 2138 Application/Control Number: 18/965,499 Page 17 Art Unit: 2138
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