DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/24/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 5 and 18 are objected to because of the following informalities: the claims recite an acronym “SFQ” for the first time in the claim tree. The meaning of the acronym needs to be specified as is done for RQL in claim 2 in order to avoid potential confusions. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9, 11, 13, 14, 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dai (US 9,876,505 B1).
Regarding claim 1, Dai teaches an isochronous phase-drift tracking receiver system (Fig. 1, 14, col. 3, lines 14-15, a receiver system 14) configured to receive a sequence of pulses from a transmitter system (col. 3, lines 18-20, a sequence of data pulses) that operates from a first clock signal via a transmission line (col. 3, line 20, a sequence of data pulses across the transmission line 16), to initially align the sequence of pulses to a defined phase of a second clock signal (col. 3, lines 8-12, accommodate an unknown or arbitrary phase relation between clock signals), and to generate a phase-tracking signal having a first state that is indicative of a phase of the sequence of pulses being aligned to the defined phase of the second clock signal and a second state that is indicative of the phase of the sequence of pulses being misaligned to the defined phase of the second clock signal (Fig. 5, col. 10, lines 4-6,
R
Q
L
O
U
T
aligned to the sampling phase of the clock signal CLK).
Regarding claim 2, all the limitations of claim 1 are taught by Dai.
Dai further teaches the system, comprising a phase-drift receiver (Fig. 1, 14, Receiver System) configured to receive the sequence of pulses (PLS) from the transmitter system (10, Transmitter System) via the transmission line (16) and to generate a phase-alignment signal (Fig. 3,
R
Q
L
0
,
90
,
180
,
270
) corresponding to sequence of reciprocal quantum logic (RQL) pulses indicative of the sequence of pulses being aligned to the defined phase of the second clock signal (Fig. 3, CLK, Fig. 4,
C
L
K
Y
).
Regarding claim 3, all the limitations of claim 2 are taught by Dai.
Dai further teaches the system, wherein the phase-alignment signal corresponds to the phase-tracking signal (Fig. 5, col. 10, lines 9-17,the selector logic stage 158 continuously perform logic-AND operations…to produce a single data output that is aligned with a given one phase of the AC clock signal CLK).
Regarding claim 5, all the limitations of claim 2 are taught by Dai.
Dai further teaches the system, wherein the phase-drift receiver comprises:
an SFQ receiver configured to receive each of the sequence of pulses and to generate an SFQ pulse (Fig. 1, SFQ receiver 22, col. 4, lines 12-15);
an SFQ splitter stage (Fig. 3, 102, SFQ Splitter stage) configured to split the SFQ pulse into a plurality of SFQ pulses (SQF1-4);
a plurality of SFQ-RQL converters (Fig. 3, 104, converter system) that are each configured to sample one of the SFQ pulses at a respective phase of the second clock signal to generate at least one RQL signal (RQL0-270); and
digital logic configured to generate the phase-alignment signal that is aligned with the second clock signal based on the at least one RQL signal (Fig. 3, 106).
Regarding claim 6, all the limitations of claim 5 are taught by Dai.
Dai further teaches the system, wherein the digital logic comprises:
an alignment logic stage (Fig. 5, 152) configured to phase-align and delay each of the at least one RQL signal to provide a first at least one phase-aligned and delayed RQL signal and a second at least one phase-aligned and delayed RQL signal (Fig. 5, 152, col. 7, lines 45-49, col. 8, lines 9-12);
a waveform analysis logic stage (Fig. 5, 156) configured to latch the first at least one phase-aligned and delayed RQL signal in response to at least one trigger signal to provide a latched at least one RQL signal (col. 9, lines 38-44); and
a selector logic stage (Fig. 5, 158) configured to align one of the latched at least one RQL signal to the defined phase of the second clock signal based on the second at least one phase-aligned and delayed RQL signal to provide the phase-alignment signal (col. 9, line 67 – col. 10, line 6).
Regarding claim 7, all the limitations of claim 6 are taught by Dai.
Dai further teaches the system, wherein the transmission line is a first transmission line of a plurality of transmission lines, wherein the transmission lines have an approximately same physical length (Fig. 10, 350, col. 13, lines 5-6, bus receiver system 350), wherein the selector logic stage comprises:
a set of AND-gates to provide AND-operations on the latched at least one RQL signal and the second at least one phase-aligned and delayed RQL signal to provide first AND-outputs and a delayed AND-output (Fig. 6, AND gate 1);
a set of cascaded OR-gates configured to provide OR-operations on the first AND-outputs to provide an OR-output (Fig. 6, OR gates 1 and 2); and
an output OR-gate configured to provide an OR-operation on the OR-output and the delayed AND-output to generate the phase-alignment signal (Fig. 6, the final OR gate 2).
Regarding claim 9, all the limitations of claim 6 are taught by Dai.
Dai further teaches the system, further comprising a control logic stage (Fig. 5, 154) configured to receive an alignment signal (ALGN) and to generate the at least one trigger signal (TRG) in response to the alignment signal and at least one of the phase-aligned and delayed RQL signals (Fig. 5, DLY1).
Regarding claim 11, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 11 is rejected under the same rationale as claim 1 above.
Regarding claim 13, this claim has substantially the same subject matter as that in claim 6. Therefore, claim 13 is rejected under the same rationale as claim 6 above.
Regarding claim 14, this claim has substantially the same subject matter as that in claim 7. Therefore, claim 14 is rejected under the same rationale as claim 7 above.
Regarding claim 16, Dai teaches an isochronous phase-drift tracking receiver system (Fig. 1, 10) comprising:
a transmitter system comprising a phase-drift tracking transmitter configured to generate a sequence of pulses (Fig. 1, 12);
a transmission line to transmit the sequence of pulses from the transmitter system (Fig. 1, 16); and
a receiver system (Fig. 1, 14, col. 3, lines 14-15, a receiver system 14) comprising an isochronous phase-drift tracking receiver system configured to receive a sequence of pulses from the transmitter system (col. 3, lines 18-20, a sequence of data pulses) that operates from a first clock signal via the transmission line (col. 3, line 20, a sequence of data pulses across the transmission line 16), to initially align the sequence of pulses to a defined phase of a second clock signal (col. 3, lines 8-12, accommodate an unknown or arbitrary phase relation between clock signals), and to generate a phase-tracking signal having a first state that is indicative of a phase of the sequence of pulses being aligned to the defined phase of the second clock signal and a second state that is indicative of the phase of the sequence of pulses being misaligned to the defined phase of the second clock signal (Fig. 5, col. 10, lines 4-6,
R
Q
L
O
U
T
aligned to the sampling phase of the clock signal CLK).
Regarding claim 17, this claim has substantially the same subject matter as that in claim 2. Therefore, claim 17 is rejected under the same rationale as claim 2 above.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 5. Therefore, claim 18 is rejected under the same rationale as claim 5 above.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 7. Therefore, claim 20 is rejected under the same rationale as claim 7 above.
Allowable Subject Matter
Claims 4, 8, 10, 12, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior arts fail to teach or reasonably suggest an isochronous phase-drift tracking system comprising: a pulse generator configured to generate a sequence of reference pulses at the defined phase of the second clock signal; and an XOR gate configured to provide an XOR operation on the phase-alignment signal and the sequence of reference pulses to generate the phase-alignment signal, in combination with the other limitations of the claim.
Regarding claim 8, the prior arts fail to teach or reasonably suggest an isochronous phase-drift tracking system wherein the transmission line is a first transmission line of a plurality of transmission lines, wherein the transmission lines have varying physical length, wherein the selector logic stage comprises: a set of XOR-gates to provide XOR-operations on the latched at least one RQL signal and the second at least one phase-aligned and delayed RQL signal to provide XOR-outputs; and an output OR-gate configured to provide an OR-operation on the XOR-outputs to generate the phase-alignment signal, the phase-alignment signal corresponding to the phase-tracking signal, in combination with the other limitations of the claim.
Regarding claim 10 wherein the digital logic is configured to phase-align and delay the at least one RQL signal to generate phase-aligned and delayed RQL signals, and to perform XOR-operations on the phase-aligned and delayed RQL signals to generate the phase-alignment signal, the phase-alignment signal corresponding to the phase-tracking signal, in combination with the other limitations of the claim.
Regarding claim 12, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 12 is objected to under the same rationale as claim 4 above.
Regarding claim 15, this claim has substantially the same subject matter as that in claim 10. Therefore, claim 15 is objected to under the same rationale as claim 10 above.
Regarding claim 19, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 19 is objected to under the same rationale as claim 8 above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sarda (US 20210157356 A1) see Figures 3 and 4 discloses an XOR gate configured to provide an XOR operation on a reference clock to perform edge detection, however does not clearly teach its application on/relationship to a transmitter-receiver system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEOKJIN KIM/Primary Examiner, Art Unit 2845
Prosecution Insights