DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Re 112 issue, This has been resolved for claims 8 and 9.
Re claims 1, 8, 9 and 20, the examiner maintains the rejection under 35U.S.C. 102(a)(2) with re Dupuis reference. As figures 2 and 7 show and the brief description of such, this is a digital isolator system for digital communications. The delay path is shown in figure 7 as noted in the rejection as follows: See below for FINAL REJECTION.
Similarly, for the Crawley et al reference the examiner maintains the rejection on claims 1 and 20 with regards the digital isolator shown in figure 1C with delay path.
The delay paths of both references delay the COMMON/same input DATA and this delay is passed thru to the output(s); that is, it does not matter, for all intents and purpose(s), the second output of the TX’r is delayed. Nothing in the claim points to any difference in transmitter output signals. Also, TIPO patent grant has no relevancy to this prosecution as examiner interprets the claims at hand in light of the references applied in this prosecution.
An interview is requested to advance prosecution.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 9 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dupuis et al(US Pat 9,923,643) of record.
The reference to Dupuis et al, see figure 7 below, showing digital isolator module with additional delay path,
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A transmitter circuit(602) receives a data input signal (DATA)and generates a first transmitter output signa(output of block 612 receiving DATA_ONE) and a second transmitter output signal(output of 612 receiving DATA_ZERO) in response to the data input signa(DATA).
The second transmitter output signal is a delay signal of the first transmitter output signal due to the delay path identified in the figure.
An isolation barrier(606) is coupled to the transmitter circuit(602 w/612) and receiving the first transmitter output signal and the second transmitter output signal.
The isolation barrier(606) is operable to develop a first isolated output signal (INPUT TO 614 to produce RDATA_ONE)and a second isolated output signal (INPUT TO 614 to produce RDATA_TWO))respectively in response to the first transmitter output signal and the second transmitter output signal.
A receiver circuit(604), coupled to the isolation barrier and receiving the first isolated output signal and the second isolated output signal, such that the receiver circuit is operable to generate a data output signal (RDATA)in response to the first isolated output signal and the second isolated output signal.
Re claims 8 and 9(as best understood):
Please see waveforms for the transmitter(first and second) output signals, periodic signals, as the voltage level of the data input signal(s) is/are repeated.
Re claim 20, please see figure above for the isolation barrier pair(s) of capacitors between the transmitter outputs and the respective isolator outputs prior to receiver side. A digital isolator system.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Crawley et al(US Pat 7,923,710) of record.
The reference to Crawley et al, see figure 1C below, showing digital isolator system module with additional delay path,
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A transmitter circuit(transmitter) receives a data input signal (INPUT)and generates a first transmitter output signa(output at CP1) and a second transmitter output signal(output of additional delay path) in response to the data input signa(INPUT).
As shown, the second transmitter output signal is a delayed signal of the first transmitter output signal due to the delay path identified in the figure.
An isolation barrier(isolator) is coupled to the transmitter circuit(transmitter) and receiving the first transmitter output signal and the second transmitter output signal.
The isolation barrier(isolator) is operable to develop a first isolated output signal (INPUT TO CP2 at + terminal of the AMP)and a second isolated output signal (INPUT TO CP2 at the – terminal of AMP)respectively in response to the first transmitter output signal and the second transmitter output signal. A digital isolator system.
A receiver circuit(including AMP), coupled to the isolation barrier and receiving the first isolated output signal and the second isolated output signal, such that the receiver circuit is operable to generate a data output signal (output of 126)in response to the first isolated output signal and the second isolated output signal.
Re claim 20, please see figure above for the isolation barrier pair(s) of capacitors between the transmitter outputs and the respective isolator outputs prior to receiver side.
Allowable Subject Matter
Claims 2-7 and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
Prosecution Insights