Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 1-2, 7, 19-200031-0035 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20080291349 A1) in view of Hwang (US 20150009109 A1).
Regarding claim 1:
Kim (US 20080291349 A1) discloses a display substrate (Fig. 5), comprising:
a base substrate (110) ([0058-0060]);
a plurality of light emitting devices (pixel with OLED, Fig.3A) provided on the base substrate ([0037-0040]); a plurality of pixel circuits (PX, Fig. 1-2) provided on the base substrate for driving the plurality of light emitting devices to emit light ([0037-0040]), wherein the plurality of pixel circuits are arranged in an array in a first direction and a second direction (pixels in metrics, see Fig. 1-2) [0037-0040]);
and a plurality of groups of data lines (Dm) provided on the base substrate [0037-0040], wherein the plurality of groups of data lines are arranged in the first direction, and at least one column of pixel circuits ( see Fig. 1) is electrically connected to at least one group of data lines ([0031-0035]), wherein the at least one column of pixel circuits (PX) comprises a first pixel circuit (PX) and a second pixel circuit alternately arranged in the second direction (see Fig. 1), each of the first pixel circuit and the second pixel circuit comprises an input transistor (T1) (Fig. 3A, [0037-0038]), and the at least one group of data lines comprises a first data line (DL1) and a second data line (DL2) ([0037-0038]).
Note that Kim does not specifically discloses wherein the first data line and the second data line are respectively located on two sides of the first pixel circuit and the second pixel circuit.
Hwang (US 20150009109 A1) discloses wherein the first data line (DL on the left ) and the second data line (DL on the right) are respectively located on two sides of the first pixel circuit (P1) and the second pixel circuit (P2) ([0058-0059], Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teaching of Hwang, thereby reliability of a display device could be improved.
Regarding claim 2:
Kim in view of Hwang discloses a plurality of first power lines (positive polarity (+) data signals and at the same time a (4N-2)-th data line DL4N-2 is connected to remaining pixels in the same pixel column PCm which will be driven with positive negative (-) data signals, [0043], see [0043]) provided on the base substrate (display substrate, see Fig. 2), wherein the plurality of first power lines are arranged in the first direction, and at least one column of pixel circuits is electrically connected to at least one first power line (see [0058-0059], Fig. 2), wherein for the at least one column of pixel circuits, the data lines electrically connected to the column of pixel circuits, and the first power line electrically connected to the column of pixel circuits ([0058-0059], Fig. 2), the input transistor (T1) of the first pixel circuit is electrically connected to the first data line (see Fig. 1, [0045]), and the input transistor of the second pixel circuit is electrically connected to the second data line (see Hwang Fig. 2, [0058-0059]); and
Wang in view of Hwang discloses wherein an orthographic projection of the first data line (DL) on the base substrate (display substrate), an orthographic projection of the first power line on the base substrate and an orthographic projection of the second data line on the base substrate are arranged in sequence in the first direction (see Hwang Fig. 2, [0058-0059]) , an orthographic projection of the input transistor of the first pixel circuit on the base substrate is located on a side of the orthographic projection of the first power line on the base substrate close to the orthographic projection of the first data line on the base substrate (see Wang (see Fig. 3) [0044-0046]; and Hwang Fig. 1-2,[0045] [0058-0059]), and
an orthographic projection of the input transistor of the second pixel circuit on the base substrate is located on a side of the orthographic projection of the first power line on the base substrate close to the orthographic projection of the second data line on the base substrate (see Wang (see Fig. 3) [0044-0046]; and Hwang Fig. 1-2, [0045] [0058-0059]) (same motivation as applied to claim 1).
Regarding claim 19-20:
Kim a display panel, comprising the display substrate ([0035-0038], Fig. 1).
Regarding claim 7:
Kim in view of Hwang disclose at least one first scanning signal line (L1),plurality of pixels and the input transistor is electrically connected to the data line, a gate electrode of the input transistor is electrically connected to the at least one first scanning signal line ((see wang Fig. 2, [0040], [0044-0046]).
Kim discloses at least one pixel circuit in the plurality of pixel circuits further comprises a driving transistor (T2) and a storage capacitor (Cst) (see Fig. 3B); and wherein in the at least one pixel circuit, a first electrode of , a first electrode of the driving transistor (T1) is electrically connected to a second electrode of the input transistor ([0037-0040]), a second electrode of the driving transistor is electrically connected to a first electrode of a light emitting device (OLED), a gate electrode of the driving transistor is electrically connected to a first electrode plate (i.e. lower electrode 120) of the storage capacitor (Cst)through a first connecting hole (130), and a second electrode plate (upper electrode 140) of the storage capacitor is electrically connected to the first power line (VDD) (see Kim, [0082-0084], Fig. 4). Same motivation as recited in claim 1.
Allowable Subject Matter
2. Claims 3-6 and 8-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3:
The closest art of record singly a first gate metal layer (GT1, Fig. 9) provided on a side of the semiconductor layer away from the base substrate, a first conductive layer (SD1, Fig. 17) provided on a side of the first gate metal layer away from the base substrate, a second conductive layer (SD2, see Fig. 17) provided on a side of the first conductive layer away from the base substrate, and a third conductive layer (SD3, Fig. 19) provided on a side of the second conductive layer away from the base substrate; wherein the display substrate further comprises at least one first reset signal line (signal line at first transistor T3), at least one second reset signal line (signal line at first transistor T7) and at least one third reset signal line (signal line at first transistor T8) that are located in the third conductive layer; and wherein the orthographic projection of the first data line on the base substrate is located between the first reset signal line and the first power line, or the orthographic projection of the first data line on the base substrate is located between the second reset signal line and the first power line, or the orthographic projection of the first data line on the base substrate is located between the third reset signal line and the first power line (see Applicant discloser Fig. 6 , 0067, 0082, 0099, 0075-0080].
Regarding claim 8:
Kim discloses wherein for the at least one column of pixel circuits (D), the input transistor of the first pixel circuit after being translated in the second direction is mirror symmetrical with the input transistor of the second pixel circuit about a first axis, the first axis extends in the second direction, and the first connecting hole is located on the first axis (see Applicant’s disclosure [0068-0072], Fig. 4).
Pertinent art
3. Pertinent art of record Hyafuji (US 20050190128 A1), Ryu (US 20200394381 A1) and Zhang (US 20210174746 A1) discloses display device.
Inquiry
5. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao could be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHEDA A ABDIN/Primary Examiner, Art Unit 2627