DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on April 21st, 2025, have been carefully considered.
Claims 1-20 have been canceled.
Claims 21-36 have been added as new.
Clams 21-36 are currently pending in the instant application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 24-26, and 29-36 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-6, 8-9, and 12-13 of U.S. Patent No. 10,067,864. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 10,067,864 contains every element of claim 21 of the instant application and as such anticipates claim 21 of the instant application.
Claim 2 of U.S. Patent 10,067,864 contains every element of claim 24 of the instant application and as such anticipates claim 24 of the instant application.
Claim 3 of U.S. Patent 10,067,864 contains every element of claim 25 of the instant application and as such anticipates claim 25 of the instant application.
Claim 5 of U.S. Patent 10,067,864 contains every element of claim 26 of the instant application and as such anticipates claim 26 of the instant application.
Claim 6 of U.S. Patent 10,067,864 contains every element of claim 36 of the instant application and as such anticipates claim 36 of the instant application.
Claim 8 of U.S. Patent 10,067,864 contains every element of claims 32-33 of the instant application and as such anticipates claims 32-33 of the instant application.
Claim 9 of U.S. Patent 10,067,864 contains every element of claims 34-35 of the instant application and as such anticipates claims 34-35 of the instant application.
Claim 12 of U.S. Patent 10,067,864 contains every element of claim 29 of the instant application and as such anticipates claim 29 of the instant application.
Claim 13 of U.S. Patent 10,067,864 contains every element of claims 30-31 of the instant application and as such anticipates claims 30-31 of the instant application.
Claims 21, and 27-35 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 9-12, and 14-16 of U.S. Patent No. 10,891,220. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 10,891,220 contains every element of claim 21 of the instant application and as such anticipates claim 21 of the instant application.
Claim 2 of U.S. Patent 10,891,220 contains every element of claim 27 of the instant application and as such anticipates claim 27 of the instant application.
Claim 4 of U.S. Patent 10,891,220 contains every element of claim 28 of the instant application and as such anticipates claim 28 of the instant application.
Claim 9 of U.S. Patent 10,891,220 contains every element of claim 32 of the instant application and as such anticipates claim 32 of the instant application.
Claim 10 of U.S. Patent 10,891,220 contains every element of claim 33 of the instant application and as such anticipates claim 33 of the instant application.
Claim 11 of U.S. Patent 10,891,220 contains every element of claim 34 of the instant application and as such anticipates claim 34 of the instant application.
Claim 12 of U.S. Patent 10,891,220 contains every element of claim 35 of the instant application and as such anticipates claim 35 of the instant application.
Claim 14 of U.S. Patent 10,891,220 contains every element of claim 29 of the instant application and as such anticipates claim 29 of the instant application.
Claim 15 of U.S. Patent 10,891,220 contains every element of claim 30 of the instant application and as such anticipates claim 30 of the instant application.
Claim 16 of U.S. Patent 10,891,220 contains every element of claim 31 of the instant application and as such anticipates claim 31 of the instant application.
Claims 21, 24-26, and 29-36 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-6, 8-9, and 12-14 of U.S. Patent No. 11,500,765. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 11,500,765 contains every element of claim 21 of the instant application and as such anticipates claim 21 of the instant application.
Claim 2 of U.S. Patent 11,500,765 contains every element of claim 24 of the instant application and as such anticipates claim 24 of the instant application.
Claim 3 of U.S. Patent 11,500,765 contains every element of claim 25 of the instant application and as such anticipates claim 25 of the instant application.
Claim 5 of U.S. Patent 11,500,765 contains every element of claim 26 of the instant application and as such anticipates claim 26 of the instant application.
Claim 6 of U.S. Patent 11,500,765 contains every element of claim 36 of the instant application and as such anticipates claim 36 of the instant application.
Claim 8 of U.S. Patent 11,500,765 contains every element of claims 32-33 of the instant application and as such anticipates claims 32-33 of the instant application.
Claim 9 of U.S. Patent 11,500,765 contains every element of claims 34-35 of the instant application and as such anticipates claims 34-35 of the instant application.
Claim 12 of U.S. Patent 11,500,765 contains every element of claim 29 of the instant application and as such anticipates claim 29 of the instant application.
Claim 13 of U.S. Patent 11,500,765 contains every element of claim 30 of the instant application and as such anticipates claim 30 of the instant application.
Claim 14 of U.S. Patent 11,500,765 contains every element of claim 31 of the instant application and as such anticipates claim 31 of the instant application.
Claims 21, 24-26, and 28-36 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-8, 11-13, and 15 of U.S. Patent No. 12,197,319. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of U.S. Patent 12,197,319 contains every element of claim 21 of the instant application and as such anticipates claim 21 of the instant application.
Claim 2 of U.S. Patent 12,197,319 contains every element of claim 24 of the instant application and as such anticipates claim 24 of the instant application.
Claim 3 of U.S. Patent 12,197,319 contains every element of claim 25 of the instant application and as such anticipates claim 25 of the instant application.
Claim 5 of U.S. Patent 12,197,319 contains every element of claim 36 of the instant application and as such anticipates claim 36 of the instant application.
Claim 6 of U.S. Patent 12,197,319 contains every element of claim 26 of the instant application and as such anticipates claim 26 of the instant application.
Claim 7 of U.S. Patent 12,197,319 contains every element of claims 32-33 of the instant application and as such anticipates claims 32-33 of the instant application.
Claim 8 of U.S. Patent 12,197,319 contains every element of claims 34-35 of the instant application and as such anticipates claims 34-35 of the instant application.
Claim 11 of U.S. Patent 12,197,319 contains every element of claim 29 of the instant application and as such anticipates claim 29 of the instant application.
Claim 12 of U.S. Patent 12,197,319 contains every element of claim 30 of the instant application and as such anticipates claim 30 of the instant application.
Claim 13 of U.S. Patent 12,197,319 contains every element of claim 31 of the instant application and as such anticipates claim 31 of the instant application.
Claim 15 of U.S. Patent 12,197,319 contains every element of claim 28 of the instant application and as such anticipates claim 28 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-28 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Elder et al. [US2015/0050678] in view of Flake et al. [US7596721]. Elder teaches modular analytical test meter. Flake teaches methods and structure for patching embedded firmware.
Regarding claim 21, Elder teaches a method of producing an analyte monitoring device [Elder paragraph 0002, first lines “…Analyte detection in physiological fluids…”], wherein the analyte monitoring device comprises a processor [Elder figure 2c, feature 172 “Microcontroller”] adapted to execute application software [Elder paragraph 0111 “404 Software”], a writable memory [Elder paragraph 0089 “162 RAM module”], and a non-transitory read-only memory (ROM) [Elder paragraph 0090, “ROM module”] having a function lookup data structure and a first function stored thereon [Elder paragraph 0039, first lines “…the analytical plug-in module 104 may store one or more firmware updates thereon with corresponding firmware codes…”], wherein the function lookup data structure comprises an identifier for the first function and a first address of where the first function is stored [Elder paragraph 0039, first lines “…such as a numerical identifier…”], the method comprising:
inputting a revision lookup data structure into the writable memory [Elder paragraph 0037, last lines “…The firmware update may be stored in an EEPROM, ROM, or Flash memory provided with the analytical module 104 as a code image 306. An example of an authorized firmware update may include the addition of a software based bolus calculator for patients who also wear an insulin patch and desire to use the tool for tracking insulin use patterns and remaining insulin dosages…”],
Elder fails to explicitly teach wherein the revision lookup data structure includes the identifier for the first function and a second address of where a replacement function for the first function is stored.
However, Flake does teach wherein the revision lookup data structure includes the identifier for the first function and a second address of where a replacement function for the first function is stored [Flake figure 1, feature 106 “Patch memory” , “Patch Value”, and “Patch Address” and column 6, lines 25-28 “…patch memory 106 may include a plurality of patch address values 120 through 126 and corresponding patch data values 130 through 136…”(The examiner has determined the patch address reads on the identifier of the first function and is replaced with the second address of the patch value.)].
Elder and Flake are analogous arts in that they both deal with updating firmware.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Elder’s firmware update with Flake’s address matching when patching firmware for the benefit of reducing the potential for undesired execution and/or memory fetch overhead [Flake column 3, lines 6-9 “…improved firmware patch structures and methods that are, at once, simple and inexpensive and reduce undesirable execution or memory fetch overhead.…”].
copying the function lookup data structure from the ROM to the writable memory [Elder paragraph 0039, middle lines “…a bootstrap loader 304 pushes the code image over the module electrical interface 137 which is stored and installed for use in the meter chassis 10…” and paragraph 0037, first lines “…The firmware update may be stored in an EEPROM, ROM, or Flash memory provided with the analytical module 104…”];
verifying an integrity of data in the revision lookup data structure after the analyte monitoring device has been activated [Elder paragraph 0039, first lines “…may store one or more firmware updates thereon with corresponding firmware codes, such as a numerical identifier, corresponding to one or more different chassis types. Upon insertion into, and electrical engagement with, a meter chassis 108, a programmed protocol may be initiated in the meter chassis 108 or in the analytical module 104 whereby the firmware codes and meter chassis types, which may be another numerical identifier stored on the chassis side, are compared and verified so that only authorized updated platform or tool versions may be installed in the meter chassis 108.…”]
determining if the revision lookup data structure includes the identifier for the first function if the integrity of the data is verified [Elder paragraph 0045, last lines “…If the inserted module's firmware code or module ID is determined by the processing unit 172 as being an authorized and compatible module, at step 603, firmware corresponding to the test meter 100 type is transmitted over the mechanical and electrical interface using the module's bootstrap loader for installation by the processing unit 172 at step 605…”]; and
Flake teaches replacing the first address with the second address in the function lookup data structure copied to the writable memory if the identifier for the first function is included in the revision lookup data structure [Flake column 5, lines 30-50 “…Patch memory 106 provides patch information to be substituted for data normally read/fetched from program memory 104 in response to read/fetch operations by processor 102. Patch memory 106 receives the memory read address from address bus 190 in parallel with program memory 104. If patch memory 106 identifies a matching address corresponding to the applied read address on bus 190, alternative or patch data is applied to bus 198 and a signal is applied to match detect 194 to so indicate the detected address match. The match detect 194 signal is applied as a select input to multiplexer 140 to select patch data on bus 198 for application to data bus 192…Patch memory 106 therefore substitutes values in place of actual read data in response to a read access to program memory 104 by processor 102. Patch memory 106 detects address matches and substitutes patch data, if appropriate, within the timing constraints of normal read cycle timing of program memory 104….” and column 2, lines 19-30 “…The fixed, reserved RAM location corresponding to the desired function or subroutine would normally contain a second program instruction to jump into the actual desired function or subroutine in the ROM or may contain an address for the function to be performed. In the latter case, the address is read by the processor and then an indirect jump to that location may be performed. Patching firmware in such a structure is a simple matter of replacing the second jump instruction (or address) in the reserved RAM location with the new function (either as a jump instruction to the updated function or an address of the new function to be loaded and jumped to indirectly)…” and column 2, lines 38-43 “…a full mirrored memory component, equal in size to the ROM to be patched, such that each memory location may be fetched from the primary ROM or from the secondary, mirrored memory containing patched versions of functions or other information…”(The examiner has determined that Flake teaches multiple techniques that read on applicant’s method of patching firmware.).
Regarding claims 22, as per claim 21, Elder teaches the method further comprises the steps of: calculating a first checksum for the revision lookup data structure after the revision lookup data structure is inputted into the writable memory, and storing the first checksum in the writable memory [Elder paragraph 0045, most lines “…The processing unit 172 may detect the insertion of the analytical module and begins a verification procedure, at step 602, whereby a firmware code or a module ID code stored in the analytical module is read and compared with a meter chassis ID stored in a memory of the meter chassis 108. If the inserted module's firmware code or module ID is determined by the processing unit 172 as not being an authorized and compatible module, at step 603, firmware is not transmitted over the mechanical and electrical interface and the analytical module 104 is not rendered operable with the test meter 100. An incompatible module may be detected if the module is an older version or if the firmware stored thereon is incompatible with the meter chassis hardware. A stored status message may then be displayed on a display screen 114 of the meter chassis 108, at step 604, to indicate to a user of the analytical test meter 100 that the analytical module 104 is not enabled. If the inserted module's firmware code or module ID is determined by the processing unit 172 as being an authorized and compatible module, at step 603, firmware corresponding to the test meter 100 type is transmitted over the mechanical and electrical interface using the module's bootstrap loader for installation by the processing unit 172 at step 605. A stored status message may then be displayed on a display screen 114 of the meter chassis 108, at step 606, to indicate to a user of the analytical test meter 100 that the test meter 100 has been updated with the new firmware…”(The examiner has determined that using checksum is a way of verifying if various entities match during a comparison. Thus Elders teaching of comparing the ID codes to determine if the modules are authorized implies the use of checksums.)].
Regarding claim 23, as per claim 21, Elder teaches verifying the integrity of data in the revision lookup data structure comprises the steps of calculating a second checksum for the revision lookup data structure after the analyte monitoring device has been activated [Elder paragraph 0045, first lines “…the analytical module 104 receives power from the meter chassis 108 power supply module 166. The processing unit 172 may detect the insertion of the analytical module and begins a verification procedure…”]; and comparing the second checksum with the first checksum, wherein the integrity of data is verified if the second checksum matches the first checksum [Elder paragraph 0045, most lines “…The processing unit 172 may detect the insertion of the analytical module and begins a verification procedure, at step 602, whereby a firmware code or a module ID code stored in the analytical module is read and compared with a meter chassis ID stored in a memory of the meter chassis 108. If the inserted module's firmware code or module ID is determined by the processing unit 172 as not being an authorized and compatible module, at step 603, firmware is not transmitted over the mechanical and electrical interface and the analytical module 104 is not rendered operable with the test meter 100. An incompatible module may be detected if the module is an older version or if the firmware stored thereon is incompatible with the meter chassis hardware. A stored status message may then be displayed on a display screen 114 of the meter chassis 108, at step 604, to indicate to a user of the analytical test meter 100 that the analytical module 104 is not enabled. If the inserted module's firmware code or module ID is determined by the processing unit 172 as being an authorized and compatible module, at step 603, firmware corresponding to the test meter 100 type is transmitted over the mechanical and electrical interface using the module's bootstrap loader for installation by the processing unit 172 at step 605. A stored status message may then be displayed on a display screen 114 of the meter chassis 108, at step 606, to indicate to a user of the analytical test meter 100 that the test meter 100 has been updated with the new firmware…”(The examiner has determined that using a first and second checksum is a way of verifying if various entities match during a comparison. Thus Elders teaching of comparing the ID codes to determine if the modules are authorized implies the use of checksums.)].
Regarding claim 24, as per claim 21, Elder teaches the writable memory comprises non-volatile and non-transitory writable memory on which the revision lookup data structure and the replacement function for the first function is stored [Elder paragraph 0030, all lines “…a non-volatile memory 163, which may comprise read only memory ("ROM") or flash memory, and a circuit 164 for connecting to an external portable memory device, for example, via a USB data port, is electrically connected to the processing unit 172 over a electrical interface 173. External memory devices may include flash memory devices housed in thumb drives, portable hard disk drives, data cards, or any other form of electronic storage devices. The on-board memory can include various embedded applications and stored algorithms in the form of programs executed by the processing unit 172 for operation of the analytical test meter 100, as will be explained below. On board memory can also be used to store a history of a user's sample analyte measurements, such as blood glucose measurements, including dates and times associated therewith. Using the wireless transmission capability of the analytical test meter 100, as described below, such measurement data can be transferred via wired or wireless transmission to connected computers or other processing devices…”].
Regarding claim 25, as per claim 21, Elder teaches the writable memory comprises non- volatile and non-transitory writable memory on which the function lookup data structure is copied from the ROM [Elder paragraph 0030, all lines “…a non-volatile memory 163, which may comprise read only memory ("ROM") or flash memory, and a circuit 164 for connecting to an external portable memory device, for example, via a USB data port, is electrically connected to the processing unit 172 over a electrical interface 173. External memory devices may include flash memory devices housed in thumb drives, portable hard disk drives, data cards, or any other form of electronic storage devices. The on-board memory can include various embedded applications and stored algorithms in the form of programs executed by the processing unit 172 for operation of the analytical test meter 100, as will be explained below. On board memory can also be used to store a history of a user's sample analyte measurements, such as blood glucose measurements, including dates and times associated therewith. Using the wireless transmission capability of the analytical test meter 100, as described below, such measurement data can be transferred via wired or wireless transmission to connected computers or other processing devices....”].
Regarding claim 26, as per claim 21, Elder teaches the analyte monitoring device comprises a sensor adapted for insertion through a skin of the subject, wherein the verifying step is performed after the sensor is inserted through the skin of the subject [Elder paragraph 0044, last lines “…According to this exemplary version, another system component 502 such as a test strip dispenser, a strip ejector or lancing device can be combined with the plug-in analytical module 504 to provide additional versatility and capability. In the depicted version, a lancing device 506 is disposed on the analytical module 504 that can be or otherwise releasably or fixedly attached onto the side surface of the meter chassis 508…”].
Regarding claim 27, as per claim 21, Elder the revision lookup data structure is inputted into the writable memory through a serial interface [Elder paragraph 0030, middle lines “…via a USB data port…”].
Regarding claim 28, as per claim 21, Elder teaches the revision lookup data structure is inputted into the writable memory through a radio frequency (RF) receiver [Elder paragraph 0031, first lines “…A wireless module 156 may include transceiver circuits for wireless digital data transmission and reception via one or more internal digital antennas 157, and is electrically connected to the processing unit 172 over electrical interface 173…”].
Regarding claim 30, as per claim 21, Elder teaches the function lookup data structure is an array or a software table [Elder paragraph 0039, first lines “…may store one or more firmware updates…”].
Regarding claim 31, as per claim 21, Elder teaches the revision lookup data structure is an array or a software table [Elder paragraph 0042, last lines “…according to software programs 404…”].
.
Allowable Subject Matter
Claims 29 and 32-36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kraft et al. [US2008/0076969] Kraft teaches upgrading the ability and software of a hand held medical device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139