DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119, which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 8-28-2025 and 10-8-2025 have been considered by the examiner (see attached PTO-1449).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/052,107 Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of the current application is an obvious variation of the claim of the co-pending application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. The table below shows the similarities and differences between claim 1 of the current application and the co-pending application.
USP 19/052,107
Current application 18/965,734
1. A decoder, comprising:
1. A decoder, comprising:
a first processing circuit is configured to:
a first processing circuit configured to:
obtain a check expression and a check expression weight based on a codeword to be decoded in a current iteration and a check matrix;
obtain a check formula and check formula weight based on a codeword to be decoded in a current iteration and a check matrix;
a second processing circuit is configured to:
a second processing circuit configured to:
obtain energy of the codeword to be decoded in the current iteration based on the check matrix, the check expression, and a flipping state of the codeword to be decoded in the current iteration;
obtain energy of the codeword to be decoded in the current iteration based on the check formula, the check matrix and a flipping state of the codeword to be decoded in the current iteration;
a processor is configured to:
a processor configured to:
determine a flipping threshold in the current iteration based on a changing state of the check expression weight; and
in a first iteration, select one of a plurality of preset threshold sequences as an initial threshold sequence based on the check formula weight; and
assign a flipping threshold in the initial threshold sequence to a bit flipping circuit; and
a bit flipping circuit is configured to:
the bit flipping circuit configured to:
output a codeword to be decoded in a next iteration based on a comparison result of the energy of the codeword to be decoded in the current iteration and the flipping threshold in the current iteration determined by the processor.
output the codeword to be decoded in a following iteration based on a result of a comparison between the energy of the codeword to be decoded in the current iteration and the flipping threshold assigned by the processor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 18 to 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiong et al. (USP 11,146,290).
Claims 1 and 11:
Xiong substantially teaches the claimed invention. Xiong teaches a bit flipping decoder (130) comprising: an obtaining module (310) (“first processing circuit” for obtaining data or information from other modules or units inside or outside the decoder (see fig. 3 and par. col 8, lines 60 to 65). Xiong teaches that the obtaining module may obtain one or more parameters that may be used in a decoding process such as a flipping energy threshold for a specific bit node, a parity check matrix cod decoding the received codeword, which reads on “obtain a check formula and check formula weight based on a codeword to be decoded in a current iteration and a check matrix” (see col. 8 lines 63 to 67). Xiong teaches that a syndrome weight calculation module (320) checks a syndrome weight of the codeword according to a parity check matrix (see col. 9, lines 3 to 7). Xiong teaches that a processing module (330) (“a second processing circuit”) may determine flipping energies of a group of bit nodes as well as determining flipping probabilities of the group of bits (see col. 9, lines 8 to 14). Xiong teaches that the processing module may compare a syndrome weight determined by the syndrome weight calculation module with a specific value to judge whether the received codeword has being properly decoded, which reads on “obtain energy of the codeword to be decoded in the current iteration based on the check formula, the check matrix and a flipping state of the codeword to be decoded in the current iteration” (see col. 9, lines 15 to 22).
Xiong teaches that a determination module (340) (“a processor”) may be configured to determine whether a preset condition is satisfied during the decoding process (see col. 9, line 23 to 26). Xiong teaches that the preset condition includes the syndrome weight being equal to a number of iterations reaching a threshold (see col. 9, lines 23 to 31). Xiong teaches that the decoder contains a flipping test module (350) (“bit flipping circuit”) that is configured to perform a flipping test on bit nodes to determine at least one target bit node that is required to be flipped (see col. 9, lines 32 to 35).
Xiong teaches that the decoder determines a decoding success by comparing the syndrome weight to the syndrome weight threshold (see fig, 5 and col. 14 lines 22 se seq.). Xiong fails to specifically teach the limitation of the decoder comprising the steps of: “assign a flipping threshold in the initial threshold sequence to a bit flipping circuit;” however, this teaching is obvious to the teachings of Xiong because Xiong teaches that a decoder for providing improved bit flipping method incudes designating an individual flipping reliability for each bit node in the bit node group and determining a flipping reliability based on received soft information (see col. 15, lines 5 et seq.).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the decoder of Xiong having a flipping reliability by replacing it with the claimed limitation of: “assign a flipping threshold in the initial threshold sequence to a bit flipping circuit” because Xiong teaches that a method and an apparatus for providing improved bit flipping decoding includes a decoder determining flipping reliabilities for the initial soft information received and performing a bit flipping test based on the determined flipping reliabilities. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for improving bit flipping decoding using either flipping threshold or a flipping reliability as taught by Xiong (see col. 2, lines 5 et seq.). As to the other limitation of the claim, Xiong teaches that flipping test results are provided to an updated hard decision module to output updated codeword (see col. 16, lines 46 dt seq.).
Claim 18:
Xiong substantially teaches the claimed invention. Xiong teaches a computer readable medium comprising a decoder in communication with an encoder via a channel (see col. 5, lines 25 to 30). Xiong teaches that a data transmission system including an encoder, a channel and a decoder comprises the encoder being installed on a transmitter and the decoder being installed on a receiver (see fig. 1 and col. 7, lines 4 to 10). Xiong teaches that the decoder (130) maybe part of a solid-state drive (SSD) controller (see col. 7, lines 25 to 30). Xiong teaches that the decoder may include a storage module for storing instructions that can be executed by a processor (see col. 9, lines 40 to 45).
Xiong teaches a bit flipping decoder (130) comprising: an obtaining module (310) (“first processing circuit” for obtaining data or information from other modules or units inside or outside the decoder (see fig. 3 and par. col 8, lines 60 to 65). Xiong teaches that the obtaining module may obtain one or more parameters that may be used in a decoding process such as a flipping energy threshold for a specific bit node, a parity check matrix cod decoding the received codeword, which reads on “obtain a check formula and check formula weight based on a codeword to be decoded in a current iteration and a check matrix” (see col. 8 lines 63 to 67). Xiong teaches that a syndrome weight calculation module (320) checks a syndrome weight of the codeword according to a parity check matrix (see col. 9, lines 3 to 7). Xiong teaches that a processing module (330) (“a second processing circuit”) may determine flipping energies of a group of bit nodes as well as determining flipping probabilities of the group of bits (see col. 9, lines 8 to 14). Xiong teaches that the processing module may compare a syndrome weight determined by the syndrome weight calculation module with a specific value to judge whether the received codeword has being properly decoded, which reads on “obtain energy of the codeword to be decoded in the current iteration based on the check formula, the check matrix and a flipping state of the codeword to be decoded in the current iteration” (see col. 9, lines 15 to 22).
Xiong teaches that a determination module (340) (“a processor”) may be configured to determine whether a preset condition is satisfied during the decoding process (see col. 9, line 23 to 26). Xiong teaches that the preset condition includes the syndrome weight being equal to a number of iterations reaching a threshold (see col. 9, lines 23 to 31). Xiong teaches that the decoder contains a flipping test module (350) (“bit flipping circuit”) that is configured to perform a flipping test on bit nodes to determine at least one target bit node that is required to be flipped (see col. 9, lines 32 to 35).
Xiong teaches that the decoder determines a decoding success by comparing the syndrome weight to the syndrome weight threshold (see fig, 5 and col. 14 lines 22 se seq.). Xiong fails to specifically teach the limitation of the decoder comprising the steps of: “assign a flipping threshold in the initial threshold sequence to a bit flipping circuit;” however, this teaching is obvious to the teachings of Xiong because Xiong teaches that a decoder for providing improved bit flipping method incudes designating an individual flipping reliability for each bit node in the bit node group and determining a flipping reliability based on received soft information (see col. 15, lines 5 et seq.).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the decoder of Xiong having a flipping reliability by replacing it with the claimed limitation of: “assign a flipping threshold in the initial threshold sequence to a bit flipping circuit” because Xiong teaches that a method and an apparatus for providing improved bit flipping decoding includes a decoder determining flipping reliabilities for the initial soft information received and performing a bit flipping test based on the determined flipping reliabilities. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for improving bit flipping decoding using either flipping threshold or a flipping reliability as taught by Xiong (see col. 2, lines 5 et seq.). As to the other limitation of the claim, Xiong teaches that flipping test results are provided to an updated hard decision module to output updated codeword (see col. 16, lines 46 dt seq.).
As per claim 19, Xiong teaches a data transmission system comprising an encoder (110) encoding a communication signal (see col. 7, lines 5 to 30).
As per claim 20, Xiong teaches that the decoder is part of a SSD controller and a the decoder storing instructions that is executed by the processors (see col. 7, lines 25 to 30 and col. 9, lines 40 to 45).
Allowable Subject Matter
Claims 2 to 10 and 12 to 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Akkem (USPAP 2022/0116058) discloses an apparatus and a method for decoding low density parity check frames.
Fainzilber et al. (USPAP 2015/0381206) discloses a multi-stage decoder that is included in a data storage device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/ Primary Examiner, Art Unit 2112