CTNF 18/965,803 CTNF 91845 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1, 8, and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12189148 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1, 8, and 15 of the instant application are anticipated by patent claims 1, 10, and 20, respectively, in that the patent claims contain all the limitations of the instant application . Application 18965803 US 12189149 Claim 1: A memory system, comprising: circuitry; Claim 1: a set of one or more power management circuits a first switching circuit configured to couple a first bus of the memory system with a second switching circuit; a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit; the second switching circuit configured to couple the circuitry with the first switching circuit, the first switching circuit and the second switching circuit configured to program the circuitry; the second switching circuit configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit, the first switching circuit and the second switching circuit for programming the set of one or more power management circuits and a second bus coupled with a controller of the memory system and configured to communicate control signals between the controller and the circuitry, wherein the second switching circuit is configured to isolate the circuitry from the second bus. a second bus coupled with the controller and configured to communicate control signals to the set of one or more power management circuits, wherein the second switching circuit is configured to isolate the set of one or more power management circuits from the second bus. Claim 8: A method, comprising: activating a first switching circuit to couple a first bus with a second switching circuit; Claim 10: A method, comprising: activating a first switching circuit to isolate a bus from a controller and to couple the bus with a second switching circuit; activating, in accordance with activating the first switching circuit, the second switching circuit to couple circuitry with the first switching circuit and to isolate the circuitry from a second bus that couples the circuitry with a controller; activating, based on activating the first switching circuit, the second switching circuit to isolate a set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit, wherein activating the second switching circuit isolates the set of one or more power management circuits from a second bus coupled with the controller and the second switching circuit; and programming the circuitry in accordance with activating the first switching circuit and the second switching circuit. and programming the set of one or more power management circuits using signals communicated via the bus based on activating the first switching circuit and the second switching circuit. Claim 15: A system, comprising: a memory system; and a programming device coupled with the memory system, wherein the memory system is configured to: Claim 20: A system, comprising: a memory system; and a programming device coupled with the memory system and configured to cause the memory system to: activate a first switching circuit of the memory system to couple a first bus of the memory system with a second switching circuit of the memory system; activate a first switching circuit to isolate a bus from a controller and to couple the bus with a second switching circuit; activate, in accordance with activation of the first switching circuit, the second switching circuit to couple circuitry of the memory system with the first switching circuit and to isolate the circuitry from a second bus of the memory system that couples the circuitry with a controller of the memory system; activate, based on activating the first switching circuit, the second switching circuit to isolate a set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit, wherein activating the second switching circuit isolates the set of one or more power management circuits from a second bus coupled with the controller and the second switching circuit; and program the circuitry via programming signals received from the programming device in accordance with activation of the first switching circuit and the second switching circuit. And program the set of one or more power management circuits using signals communicated from the programming device to the set of one or more power management circuits via the bus based on activating the first switching circuit and the second switching circuit . 08-34 AIA Claim s 1, 8, and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12189148 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1, 8, and 15 of the instant application are anticipated by patent claims 1, 10, and 20, respectively, in that the patent claims contain all the limitations of the instant application . 08-34 AIA Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 4 and 7 of U.S. Patent No. 12189148 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of the instant application are anticipated by patent US 12189148 claims 4 and 7 in that the patent claims contain all the limitations of the instant application . 08-34 AIA Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 8-9 of U.S. Patent No. 12189148 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 5 of the instant application are anticipated by patent US 12189148 claims 8-9 in that the patent claims contain all the limitations of the instant application . 08-34 AIA Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12189148 . Although the claims at issue are not identical, they are not patentably distinct from each other because claim 6 of the instant application are anticipated by patent US 12189148 claim 2 in that the patent claims contain all the limitations of the instant application . Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “the first switching circuit and the second switching circuit configured to program the circuitry”. The first and second switches can connect the circuit to the programming device where the programming device is then able to program the circuit but the switches themselves are not capable of programming the circuitry. The can only connect and disconnect circuits/buses. It is unclear how the first switching circuit and the second switching circuit configured to program the circuitry can actually program the circuitry. Claim 8 recites “in accordance with activating of the first switching circuit” in line 4 and “activating a first switching circuit” in line 2. It is unclear if the activation of the first switching circuit in line 4 relates to when the first switching circuit is activated in line 2. For examination purposes, “in accordance with activating of the first switching circuit” will be read as “in accordance with the activating of the first switching circuit”. Claim 8 recites “in accordance with activating of the first switching circuit and the second switching circuit” in line 7, “activate a first switching circuit” in line 2 and “activate a second switching circuit” in line 4. It is unclear if the activation of the first switching circuit and second switching circuit in line 7 relates to when the first switching circuit is activated line 2 and the second switching circuit is activated in line 4. For examination purposes, “in accordance with activating of the first switching circuit and the second switching circuit” line 7 will be read as “in accordance with the activating of the first switching circuit and the second switching circuit”. Claim 15 recites “in accordance with activation of the first switching circuit” in line 7 and “activate a first switching circuit” in line 5. It is unclear if the activation of the first switching circuit in line 7 relates to when the first switching circuit is activated in line 5. For examination purposes, “in accordance with activation of the first switching circuit” will be read as “in accordance with the activation of the first switching circuit”. Claim 15 recites “in accordance with activation of the first switching circuit and the second switching circuit” in line 12, “activate a first switching circuit” in line 5 and “activate a second switching circuit” in line 7. It is unclear if the activation of the first switching circuit and second switching circuit in line 12 relates to when the first switching circuit is activated line 5 and the second switching circuit is activated in line 7. For examination purposes, “in accordance with activation of the first switching circuit and the second switching circuit” line 12 will be read as “in accordance with the activations of the first switching circuit and the second switching circuit”. Claims 2-7, 9-14 and 16-20 are also rejected as incorporating the deficiencies of the claims that they are dependent upon. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHERI L HARRINGTON/ Examiner, Art Unit 2176 June 13, 2026 /JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176 Application/Control Number: 18/965,803 Page 2 Art Unit: 2176 Application/Control Number: 18/965,803 Page 3 Art Unit: 2176 Application/Control Number: 18/965,803 Page 4 Art Unit: 2176 Application/Control Number: 18/965,803 Page 5 Art Unit: 2176 Application/Control Number: 18/965,803 Page 6 Art Unit: 2176 Application/Control Number: 18/965,803 Page 7 Art Unit: 2176 Application/Control Number: 18/965,803 Page 8 Art Unit: 2176 Application/Control Number: 18/965,803 Page 9 Art Unit: 2176
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