Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 02 December 2024 for application number 19/966,033. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 15 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 20 September 2015 (Provisional 62/221,071).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02 December 2024 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 – 7, 11, 12, 19, 23, and 24 of U.S. Patent No. 12,197,509. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the conflicting application disclose the limitations required of the claims in the instant application.
Claims 1 – 15 of the instant application are compared to claims 1, 5 – 7, 11, 12, 19, 23, and 24 of Patent No. 12,197,509 in the following table:
Instant Application
Patent No. 12,197,509
Integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable ternary content addressable memory (TCAM) to store, at least in part, table data for use in association with the packet forwarding-related operations, the integrated circuit comprising:
processing hardware to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the processing hardware resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action. (claim 1)
The integrated circuit of claim 4, wherein:
the one or more packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination. (claim 6)
The integrated circuit of claim 1, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 2)
The integrated circuit of claim 1, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 3)
Integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable ternary content addressable memory (TCAM) to store, at least in part, table data for use in association with the packet forwarding-related operations, the integrated circuit comprising:
processing hardware to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the processing hardware resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing ternary table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action. (claim 4)
The integrated circuit of claim 4, wherein:
the one or more packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination. (claim 6)
The integrated circuit of claim 1, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 5)
Machine-readable instructions to be executed by an integrated circuit, the integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable ternary content addressable memory (TCAM) to store, at least in part, table data for use in association with the packet forwarding-related operations, the integrated circuit comprising processing hardware, the instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured for performance of certain operations comprising:
storing, at least in part, in the machine-readable TCAM, the table data; and
executing, by the processing hardware, compiler-produced program instructions, the compiler-produced program instructions, when executed by the processing hardware resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple tables;
at least one of the multiple tables is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries; and
the table data is configurable to indicate packet processing rules that comprise the at least one action. (claim 7)
The integrated circuit of claim 4, wherein:
the one or more packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination. (claim 6)
The machine-readable instructions of claim 7, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 8)
The machine-readable instructions of claim 7, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 9)
Machine-readable instructions to be executed by an integrated circuit, the integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable ternary content addressable memory (TCAM) to store, at least in part, table data for use in association with the packet forwarding-related operations, the integrated circuit comprising processing hardware, the instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured for performance of certain operations comprising:
storing, at least in part, in the machine-readable TCAM, the table data; and
executing, by the processing hardware, compiler-produced program instructions, the compiler-produced program instructions, when executed by the processing hardware resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing ternary table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple tables;
at least one of the multiple tables is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries; and
the table data is configurable to indicate packet processing rules that comprise the at least one action. (claim 10)
The machine-readable instructions of claim 10, wherein:
the one or more packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination. (claim 12)
The machine-readable instructions of claim 10, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 11)
A network switch for performing packet forwarding-related operations related to a network and incoming packet data to be received via the network, the network switch being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the network switch comprising:
ports to be coupled to the network; and
an integrated circuit coupled to the ports, the integrated circuit comprising:
other machine-readable memory for use in the packet forwarding-related operations, the machine-readable TCAM and the other machine-readable memory to store table data for use in the packet forwarding-related operations; and
processing hardware to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the processing hardware resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action. (claim 13)
The integrated circuit of claim 4, wherein:
the one or more packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination. (claim 6)
The network switch of claim 13, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 14)
The network switch of claim 13, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 15)
Integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising:
other machine-readable memory for use in the packet forwarding-related operations, the machine-readable TCAM and the other machine-readable memory to store table data for use in the packet forwarding-related operations; and
at least one processing unit to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and
the table indices are configurable to correspond, at least in part, to tree nodes. (claim 1)
The integrated circuit of claim 4, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 5)
The integrated circuit of claim 5, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 6)
Integrated circuit for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising:
other machine-readable memory for use in the packet forwarding-related operations, the machine-readable TCAM and the other machine-readable memory to store table data for use in the packet forwarding-related operations; and
at least one processing unit to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and
the table indices are configurable to correspond, at least in part, to tree nodes. (claim 1)
The integrated circuit of claim 4, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 5)
Machine-readable instructions to be executed by an integrated circuit, the integrated circuit being for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising other machine-readable memory and at least one processing unit, the other machine-readable memory being for use in the packet forwarding-related operations, the machine-readable instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured to perform certain operations comprising:
storing, in the machine-readable TCAM and the other machine-readable memory, table data for use in the packet forwarding-related operations; and
executing, by the at least one processing unit, compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and
the table indices are configurable to correspond, at least in part, to tree nodes. (claim 7)
The machine-readable instructions of claim 10, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 11)
The machine-readable instructions of claim 11, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 12)
Machine-readable instructions to be executed by an integrated circuit, the integrated circuit being for use in performing packet forwarding-related operations related to incoming packet data, the integrated circuit being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the integrated circuit comprising other machine-readable memory and at least one processing unit, the other machine-readable memory being for use in the packet forwarding-related operations, the machine-readable instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured to perform certain operations comprising:
storing, in the machine-readable TCAM and the other machine-readable memory, table data for use in the packet forwarding-related operations; and
executing, by the at least one processing unit, compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the table data is configurable to indicate packet processing rules that comprise the at least one action;
the packet processing rules are configurable to indicate one or more of:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and
the table indices are configurable to correspond, at least in part, to tree nodes. (claim 7)
The machine-readable instructions of claim 10, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 11)
A network switch for performing packet forwarding-related operations related to a network and incoming packet data to be received via the network, the network switch being configurable to use machine-readable tertiary content addressable memory (TCAM) in association with the packet forwarding-related operations, the network switch comprising:
ports to be coupled to the network; and
an integrated circuit coupled to the ports, the integrated circuit comprising:
other machine-readable memory for use in the packet forwarding-related operations, the machine-readable TCAM and the other machine-readable memory to store table data for use in the packet forwarding-related operations; and
at least one processing unit to execute compiler-produced program instructions, the compiler-produced program instructions, when executed by the at least one processing unit resulting in the integrated circuit being configured to perform the packet forwarding-related operations, the packet forwarding-related operations being configurable to comprise:
performing parallel table lookup operations to determine multiple entries in the table data that match, at least in part, at least one portion of the incoming packet data;
selecting, based upon relative priorities associated with the multiple entries, one of the multiple entries that corresponds to a highest one of the relative priorities; and
based upon the one of the multiple entries, determining at least one action to be executed in relation to the incoming packet data; wherein:
the table data is configurable to comprise multiple table data partitions;
at least one of the multiple table data partitions is configurable to indicate, at least in part, the relative priorities in association with table indices that are associated with the at least one portion of the incoming packet data;
at least one other of the multiple table data partitions is configurable to comprise the multiple entries;
the packet processing rules are configurable to indicate:
at least one packet drop;
at least one next packet hop determination; and/or
at least one forwarding port determination; and
the table indices are configurable to correspond, at least in part, to tree nodes. (claim 19)
The network switch of claim 22, wherein:
at least one additional of the multiple table data partitions is configurable to indicate respective mask data associated with respective entries; and
the respective mask data is to be applied to certain portions of the incoming packet data. (claim 23)
The network switch of claim 23, wherein:
another integrated circuit comprises the machine-readable TCAM. (claim 24)
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 15 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 15 are rejected under a Double Patenting rejection.
Allowable Subject Matter
Claims 1 – 15 would be allowable, subject to a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) with respect to each of the parents.
The following is a statement of reasons for the indication of allowable subject matter: for independent claims 1, 4, 7, 10, and 13 the prior art of record, neither anticipates, nor renders obvious performing a multi table lookup operation to determine that the multiple entries in the table data (with multiple table data partitions that indicated relative priorities and packet processing rules) match a portion of incoming packet data, and based on the relative priorities of each of the multiple table entries, the entry the corresponds with the highest of the relative priorities is selected for the determination of the action for packet processing execution in relation to the incoming packet data for packet forwarding-related operations in association with TCAM (tertiary content addressable memory). The prior art of record teaches the use of TCAM and table lookup operations to determine multiple entries in the table data that match, however it does not teach performing a multi table lookup to determine table data (with multiple table data partitions that indicated relative priorities and packet processing rules) entries that match a portion of the incoming packet data, and based on the relative priorities of the table entries, the entry with the highest of the relative priorities is selected for the determination of the action for execution in relation to the incoming packet data for packet forwarding-related operations. Claims 2, 3, 5, 6, 8, 9, 11, 12, 14, and 15 depend from claims 1, 4, 7, 10, and 13 and would be allowable based on the their dependency.
The prior art made of record and not relied upon considered pertinent to applicant's disclosure.
Chen, US Pub. No. 2015/0039823 A1 – teaches “FIG. 1 is a diagram illustrating a table lookup apparatus according to a first embodiment of the present invention. In this embodiment, the table lookup apparatus 100 includes a content-addressable memory (CAM) based device 102, a cache 104 and a cache controller 106. For example, the CAM based device 102 may be implemented using a TCAM 110 with a plurality of TCAM entries (also known as TCAM rows or TCAM words) 112 and a priority encoder 114, where each TCAM entry stores a data word (e.g., WORD.sub.0-WORD.sub.n) and has a comparator (e.g., CMP.sub.0-CMP.sub.n). When an input search key SK is received by the TCAM 110, the input search key SK is compared with each data word by the corresponding comparator...” [para. 0029]
Gupta et al., US Patent No. 7,904,642 B1 – teaches “SRAM 120 includes a plurality of storage locations (e.g., rows of memory cells) for storing ACL label information generating in accordance with embodiments of the present invention. SRAM 120 includes an address input to receive IDX from TCAM device 110, and includes an output to provide a corresponding result (RST) to control logic 130. SRAM 120 can be any well-known SRAM device. For other embodiments, RAM 120 can be a DRAM or SDRAM device. For still other embodiments, SRAM 120 can be another type of addressable memory device such as Flash memory, EPROM, and so on.” [col. 5, lines 22-32]
Estan et al., US Pub. No. 2013/0246698 A1 – teaches “In the third parallel path 234, a TCAM lookup is performed in DBA 222 to yield an index of a matching data entry. Unlike in DBA 202 and 202, the TCAM accessed by DBA 222 stores the entirety of each of the outlier data entries. The index is then used in IT 224 to map to an address in a RAM. In UDA 226, the address determined in IT 224 is used to access information such as priority information regarding the matching data entry returned by DBA 222.” [para. 0050].
Giambalvo, US Pub. No. 2004/0143701 Al. – teaches “The extracted information presented to the CAM 601 over the data bus 630, along with control information over the address and control bus 620 is compared with the data stored in the CAM device 601. The result, which is the combination of a match indication and data, provided the search was successful, will aid the port processor 602 in the decision making process of whether to accept an incoming frame or cell, and what to do with a frame or cell that is accepted. This result data may be stored and retrieved from the CAM device 601 itself, or may reside in optional associated data memory 603. If the result data is stored in the associated data memory 603, it is typical that the CAM device 601 directly controls the associated data memory 603 via the control bus 640, and the data itself is written to or read from the associated data memory 603 via the data bus 650 by the port processor.” [para. 0046].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135