DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-8, 11, & 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Miller (US 20070273340 A1).
Regarding Claim 1, Miller discloses a feedback circuit for a buck-boost converter (12, 14, 16, 18 are feedback circuits for buck-boost converter 22, Fig 1 & 3A), the buck-boost converter having an input voltage and an output voltage (Vcc and Vout, Fig 3A), the feedback circuit comprising: an error amplifier, configured to generate an error voltage according to the output voltage (18 generates error voltage Ve according to Vout, Fig 3A); a ramp generator, configured to generate a ramp voltage (12 generates Ramp 1-2, Fig 1);a first comparator, coupled to the error amplifier and the ramp generator, configured to compare the error voltage with the ramp voltage to generate a control signal (41/42 receive Ve from 18 and ramp1-2 from 12 to generate comp1 out/comp2 out, Fig 3B); and a digital control circuit (clock generator 14 and pulse width logic 16, Fig 1), coupled to the first comparator (flip flops A-D and OR gates 60 & 64 get inputs from comparators 41 and 42, Fig 3B), configured to generate a plurality of switching signals according to the control signal and a reference duty signal (16 generates control signals for the buck and boost switches according to comp1 out/comp2 out and clk/clk_b, Fig 1/3A, [0021]).
Regarding Claim 6, Miller discloses all of the limitations of claim 1, and further discloses wherein the reference duty signal is a periodic pulse signal with a duty cycle substantially equal to 50% (clk/clk_b is a 50% duty cycle because it is controlled by ramp1/2, which are identical except that they are 180 degrees out of phase, and they transition at the midpoint of the ramp signals, Fig 4-6, [0021]).
Regarding Claim 7, Miller discloses all of the limitations of claim 1, and further discloses wherein the plurality of switching signals are switched according to the reference duty signal (16 generates control signals for the buck and boost switches according to comp1 out/comp2 out and clk/clk_b, Fig 1/3A/6, [0021]).
Regarding Claim 8, Miller discloses all of the limitations of claim 1, and further discloses wherein the digital control circuit comprises: a logic circuit, configured to perform logic operation on the control signal and the reference duty signal to generate at least one of the plurality of switching signals (flip flops A-D and OR gates 60 and 64 perform logic operations on comp1 out/comp2 out and clk/clk_b to generate switching signals for 34-37, Fig 3A-B, [0031]).
Regarding Claim 11, Miller teaches a buck-boost converter (10, Fig 1), comprising: a power stage (22, Fig 1), configured to receive an input voltage to generate an output voltage (Vcc and Vout, Fig 3A); and a feedback circuit, coupled to the power stage (12, 14, 16, 18 are feedback circuits for 22, Fig 1 & 3A), comprising: an error amplifier, configured to generate an error voltage according to the output voltage (18 generates error voltage Ve according to Vout, Fig 3A); a ramp generator, configured to generate a ramp voltage (12 generates Ramp 1-2, Fig 1); a first comparator, coupled to the error amplifier and the ramp generator, configured to compare the error voltage with the ramp voltage to generate a control signal (41/42 receive Ve from 18 and ramp1-2 from 12 to generate comp1 out/comp2 out, Fig 3B); and a digital control circuit (clock generator 14 and pulse width logic 16, Fig 1), coupled to the first comparator (flip flops A-D and OR gates 60 & 64 get inputs from comparators 41 and 42, Fig 3B), configured to generate a plurality of switching signals according to the control signal and a reference duty signal (16 generates control signals for the buck and boost switches according to comp1 out/comp2 out and clk/clk_b, Fig 1/3A, [0021]).
Regarding Claim 16, it is rejected for the same reasons as stated above for claim 6.
Regarding Claim 17, it is rejected for the same reasons as stated above for claim 7.
Regarding Claim 18, it is rejected for the same reasons as stated above for claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 20130293204 A1) in view of Miller (US 20070273340 A1).
Regarding Claim 2, Lu teaches a feedback circuit for a buck-boost converter (120 is a feedback circuit for buck-boost converter 100, Fig 1), the buck-boost converter having an input voltage and an output voltage (Vin and Vout, Fig 1), the feedback circuit comprising: a ramp generator, configured to generate a ramp voltage (122 generates RAMP, Fig 1); a first comparator, coupled to the error amplifier and the ramp generator, configured to compare the error voltage with the ramp voltage to generate a control signal (123 compares EA from 121 and RAMP from 122, Fig 1); and a digital control circuit (control signal generator 125 has a logic circuit 254, Fig 1/2), coupled to the first comparator (125 connected to comparator 123, Fig 3B), configured to generate a plurality of switching signals according to the control signal and a reference duty signal (125 generates switch signals CS1-2 according to CMP from 123 and "oscillator 124 is configured to operably generate an oscillating signal OSC according to the input voltage Vin of the switching regulator 110 so that a duty ratio of the oscillating signal OSC is directly proportional to a magnitude of the input voltage Vin", Fig 2, [0021]), wherein the error voltage is only compared with the ramp voltage without being compared with another ramp voltage (EA is only compared against RAMP, Fig 1).
Lu teaches an error detector 121, but does not explicitly teach that it as an error amplifier, configured to generate an error voltage according to the output voltage.
Miller teaches a conventional error amplifier for use in a buck-boost converter (see Fig 3A) an error amplifier, configured to generate an error voltage according to the output voltage (18 generates error voltage Ve according to Vout, Fig 3A).
It would have been obvious to a person of ordinary skill in the art implementing the buck-boost converter of Lu before the effective filing date of the claimed invention to replace the generic error detector with the error amplifier of Miller with predictable results as both circuits compare an output voltage to a reference to provide an error signal.
Regarding Claim 12, it is rejected for the same reasons as stated above for claim 2.
Claims 3-5 & 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Miller (US 20070273340 A1) in view of Cohen (US 5021937 A).
Regarding Claim 3, Miller discloses all of the limitations of claim 1, and further discloses a second comparator, coupled to the ramp generator, configured to compare the ramp voltage with a reference voltage (94/85 compare ramp1/2 to a reference voltage to generate the reference duty signal and could be fed directly to 16 instead of using flip flops 88/96/100, Fig 6, [0021]).
Miller does not disclose a second comparator configured to generate the reference duty signal.
Cohen teaches a conventional PWM circuit for a DC-DC converter (see Fig 2) including a second comparator, coupled to the ramp generator, configured to compare the ramp voltage with a reference voltage to generate the reference duty signal (2 compares a sawtooth signal with a reference voltage from 4 to generate a reference duty voltage to 3, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally coupled the output of Miller's 85/94 directly to 16 (omitting flip flops 88/96/100), as taught by Cohen's PWM circuit, as it provides the advantage of a simpler circuit with fewer components and lower cost.
Regarding Claim 4, the combination of Miller and Cohen discloses all of the limitations of claim 3, and further discloses wherein the reference voltage is substantially equal to one half of a peak amplitude of the ramp voltage (Ve=0.75V is half of the ramp1/ramp2 voltage, Fig 6, [0026] of Miller).
Regarding Claim 5, the combination of Miller and Cohen discloses all of the limitations of claim 3, and further discloses wherein the buck-boost converter is operated in a buck mode when the error voltage is smaller than the reference voltage, and operated in a boost mode when the error voltage is larger than the reference voltage ("A Ve threshold level of 0.75 volts identifies the transition point between the buck mode and boost mode. Any crossing of Ve by either ramp 1 or ramp 2 below the threshold level will result in only the buck mode switching transistors switching, and any crossing of Ve by either ramp 1 or ramp 2 above the threshold level will result in only the boost mode", Fig 6, [0026] of Miller).
Regarding Claim 13, it is rejected for the same reasons as stated above for claim 3.
Regarding Claim 14, it is rejected for the same reasons as stated above for claim 4.
Regarding Claim 15, it is rejected for the same reasons as stated above for claim 5.
Claims 9-10 & 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Miller (US 20070273340 A1) in view of Lin ("A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple").
Regarding Claim 9, Miller discloses all of the limitations of claim 1, and further discloses a wherein the buck-boost converter comprises a plurality of switches respectively controlled by the plurality of switching signals, wherein the plurality of switches comprise a first switch, a second switch, a third switch and a fourth switch (34-37, Fig 3A).
Miller does not disclose wherein when the buck-boost converter is operated in a buck mode, the first switch is on and the second switch, the third switch and the fourth switch are off in a first phase and the fourth switch is on and the first switch, the second switch and the third switch are off in a second phase.
Lin ("A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple,") Lin teaches a conventional buck-boost converter (see Fig 2-3) including wherein when the buck-boost converter is operated in a buck mode, the first switch is on and the second switch, the third switch and the fourth switch are off in a first phase (phase 1 is the blue path shown in buck mode going through M1 only, Fig 2), and the fourth switch is on and the first switch, the second switch and the third switch are off in a second phase (phase 2 is the green path shown in buck mode going through M4 only, Fig 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the buck-boost converter in Miller, as taught by Lin, as it provides the advantage of removing a power switch in the output current path to achieve higher efficiency (abstract of Lin).
Regarding Claim 10, Miller discloses all of the limitations of claim 1, and further discloses a wherein the buck-boost converter comprises a plurality of switches respectively controlled by the plurality of switching signals, wherein the plurality of switches comprise a first switch, a second switch, a third switch and a fourth switch (34-37, Fig 3A).
Miller does not disclose wherein when the buck-boost converter is operated in a boost mode, the second switch is on and the first switch, the third switch and the fourth switch are off in a first phase, and the first switch and the third switch are on and the second switch and the fourth switch are off in a second phase.
Lin ("A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple,") Lin teaches a conventional buck-boost converter (see Fig 2-3) including wherein when the buck-boost converter is operated in a boost mode, the second switch is on and the first switch, the third switch and the fourth switch are off in a first phase (top/blue path is the third phase in pseudo boost mode going through M2 only, Fig 2), and the first switch and the third switch are on and the second switch and the fourth switch are off in a second phase (green path is phase 5 in pseudo boost mode going through M3 only, Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the buck-boost converter in Miller, as taught by Lin, as it provides the advantage of removing a power switch in the output current path to achieve higher efficiency (abstract of Lin).
Regarding Claim 19, it is rejected for the same reasons as stated above for claim 9.
Regarding Claim 20, it is rejected for the same reasons as stated above for claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 6/24/2026
Prosecution Insights