DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28 February, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claim 12 wherein the cache-line physical address couplet comprises a set-index field concatenated to a set-way field must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 9-24 are rejected under 35 U.S.C. 103 as being unpatentable over Robinson et al (U.S. Patent Pub. No. 2019/0266101), hereinafter referred to as Robinson, in view of Moyer et al (U.S. Patent Pub. No. 2009/0177845), hereinafter referred to as Moyer.
In regard to claim 1, Robinson teaches a processor-implemented method for cache management (¶ 0006, invention is directed to cache management) comprising: accessing a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache (see Fig. 4, item 402 GPU having multiple cores and a shared lowest level cache; ¶ 0156 discloses the processor does not have to specifically be a GPU), and wherein the shared local cache supports snoop operations (Fig. 5 shows interface between cache and main bus, including coherency manager 322 having item 541 which is shown in Fig. 6A to be a snoop processor); coupling a snoop queue to the plurality of processor cores, wherein the snoop queue is shared among the plurality of processor cores (¶ 0063, snoop requests are handled by coherency manager; ¶ 0095, snoop requests may be placed in a queue; since the coherency manager managed the shared lowest level cache, the snoop queue is shared among the cores); receiving two or more snoop operations for the shared local cache, wherein the two or more snoop operations point to a common cache-line physical address within the shared local cache (¶ 0096, lines 1-3 multiple snoop requests may be received for a specific cache line), and wherein the two or more snoop operations are enqueued in the snoop queue (¶ 0095, snoop requests may be placed in a queue); generating a snoop response to a first snoop operation of the two or more snoop operations (¶ 0096, lines 3-5 disclose a counter is manipulated for each snoop response from a request); and preventing a cache eviction operation from completing, based on the snoop response being completed with a positive cache-line address comparison (¶ 0096, lines 6-8 disclose preventing an eviction of a cache line accessed by a snoop request based on other requests pending).
Robinson does not teach wherein the comparison is a physical address comparison and the cache-line physical address comparison comprises a partial cache-line physical address comparison, however Moyer ¶ 0027 disclose collapsing snoop responses directed to the same address by comparing address tag and index portions (e.g. a partial address comparison) and does not utilize virtualization, meaning the disclosure operates on physical addresses. A person of ordinary skill in the art could use this technique to enact the eviction prevention policy of Robinson as well, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Moyer in order to address issues caused by snoop requests stalling normal operation of a processor (¶ 0006, lines 2-7) and benefit from techniques for reducing snoop processing time (¶ 0030, lines 51-54).
As for claim 2, the previously cited references teach the method of claim 1. Additionally, Robinson teaches that the comparison is performed between a cache-line aligned physical address of the cache eviction operation and all cache-line aligned physical addresses of outstanding snoop entries in the snoop queue. Robinson ¶ 0096 discloses that the request counter for a cache line stores the number of outstanding requests on that item, meaning all requests must be analyzed to find matches in order to determine an accurate number. Moyer also teaches comparing cache-aligned addresses, as depicted by snoop queue circuitry in Fig. 3 including entries according to cache addresses.
As for claim 3, the previously cited references teach the method of claim 2. Additionally, Robinson teaches wherein a directory includes a snoop bit for each of the snoop entries. Cache lines in the disclosure of Robinson have translation data structures including a request counter field (¶ 0223-0224;¶ 0227 discloses request counter) which is incremented upon a snoop request and decremented upon a snoop response (¶ 0096) e.g. each cache line in the directory has at least one bit to indicate a snoop request (since the request counter must be some bit value), so each snoop request would also be associated with a bit.
As for claim 4, the previously cited references teach the method of claim 3. Additionally, Robinson teaches wherein the snoop bit is set based on a pending cache-line snoop operation in the snoop queue. As disclosed in ¶ 0096, an outstanding snoop request will result in an increment of the request counter, for example from 0 to 1, achieving the claimed limitation.
As for claim 5, the previously cited references teach the method of claim 3. Additionally, Robinson teaches wherein the snoop bit is cleared based on a last snoop replay for a pending cache-line snoop operation in the snoop queue. As disclosed in ¶ 0096, once a snoop response is generated for a request, the counter is decremented, for example from 1 to 0, achieving the claimed limitation.
As for claim 6, the previously cited references teach the method of claim 2. Additionally, Robinson teaches allowing the cache eviction operation to complete, based on the common cache-line physical address being overwritten in the shared local cache. Robinson ¶ 0140, lines 12-17 disclose 'dirty' cache lines (i.e. data modified or overwritten in the shared cache) are written back to memory, and ¶ 0138, lines 1-5 disclose that a writeback may be followed by an eviction, achieving the claimed limitation.
As for claim 9, the previously cited references teach the method of claim 1. Additionally, the cited combination teaches allowing the cache eviction operation to complete, based on the snoop response being completed with a negative cache-line physical address comparison. Robinson ¶ 0096 discloses that eviction is only restricted if a request counter is non zero. Therefore, if no snoop request is assigned to the cache line (i.e. an address comparison for the line is negative), the eviction will be allowed, achieving the claimed limitation.
As for claim 10, the previously cited references teach the method of claim 9. Additionally Robinson teaches that the negative cache-line physical address comparison indicates an absence of in-flight snoop requests for the cache-line physical address. Snoop responses are processed by accessing translation data structures (¶ 0076), therefore during normal operation, any comparison would indicate an absence of in-flight snoop requests for a line if the returned request counter is 0, including a negative comparison, achieving the claimed limitation.
As for claim 11, the previously cited references teach the method of claim 1. Additionally, Moyer teaches generating set and way data from cache line addresses (e.g. address couplets; ¶ 0017-0018). Additionally, Moyer teaches using these couplets for comparisons to determine cache hits (¶ 0021). A person of ordinary skill in the art could apply these comparisons to the combination already cited in claim 1 in order to compare snoops using couplets.
As for claim 12, the previously cited references teach the method of claim 11. Additionally, Moyer teaches that the cache-line physical address couplet comprises a set-index field concatenated to a set-way field (¶ 0018, lines 8-10 disclose determining a set using a portion of a provided address, lines 10-15 disclose determining a way using remaining address portions, these portions are concatenated together in the address). Additionally, the structure of the cache (Fig. 2) shows set and way indices for each cache item and ¶ 0017, lines 10-11 disclose that set indices are correlated to ways.
As for claim 13, the previously cited references teach the method of claim 11. Additionally, Robinson teaches comparing the cache-line physical address couplet to a snoop request physical address couplet. Robinson ¶ 0062-0065 disclose utilizing a physical address to generate a virtual address and a translation entry with several fields (e.g. a couplet having fields, bits, etc; ¶ 0064 discloses that virtual addresses are based on a known relationship) and ¶ 0076 discloses utilizing data in the translation entries to fulfill snoop requests (e.g. compare address couplets), achieving the claimed limitation.
As for claim 14, the previously cited references teach the method of claim 13. Additionally, cache eviction is only prevented if a snoop request is known to be present for a cache line (¶ 0096) which would require locating the cache line via comparison first, achieving the claimed limitation.
As for claim 15, the previously cited references teach the method of claim 11. Additionally, the cache line couplets cited in the rejection of claim 11 include data fields (see Fig. 2) which would be constant during an active snoop operation, achieving the claimed limitation.
As for claim 16, the previously cited references teach the method of claim 1. Additionally, Robinson teaches that the shared local cache is coupled to a grouping of two or more processor cores of the plurality of processor cores. See Fig. 4, cores 406 and 407 coupled via their cache to shared cache 330.
As for claim 17, Applicant is directed to the rejection of claim 16, as the limitation of a "shared local cache" already implies that the cores share the cache, and as such this limitation is already addressed.
As for claim 18, the previously cited references teach the method of claim 17. Additionally, Robinson teaches that the grouping of two or more processor cores and the shared local cache operates using local coherency. Paragraphs 0145-0147 disclose an example approach for local coherency at the cores and the shared cache, achieving the claimed limitation.
As for claim 19, the previously cited references teach the method of claim 18. Additionally, Robinson teaches that local coherency is distinct from a global coherency because global coherency requests over the memory bus utilize physical addresses, while local coherency operates on derived virtual addresses (¶ 0151 discloses the translation process for external snoops).
As for claim 20, the previously cited references teach the method of claim 19. Additionally, Robinson discloses that a modified cache line must be written back to main memory by a processor coupled to the cache holding it (¶ 0140, lines 12-17; the operation maintains cache coherency, i.e. it is a maintenance operation).
As for claim 21, the previously cited references teach the method of claim 20. Additionally, the rationale for rejection of claim 20 includes transactions between global and local coherency (writing back to the memory bus from the processor cache).
As for claim 22, the previously cited references teach the method of claim 19. Additionally, Robinson teaches that snoop requests may arrive over the memory bus for the shared local cache (i.e. global snoops are received at the local cache; ¶ 0151 discloses the translation process for external snoops).
As for claim 23, Applicant is directed to the rejection of claim 1, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 24, Applicant is directed to the rejection of claim 1, as the claims include the same limitations and are therefore rejected on the same rationale.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Robinson in view of Moyer and Reed et al (U.S. Patent Pub. No. 2022/0171712), hereinafter referred to as Reed.
As for claim 7, the previously cited references teach the method of claim 6. They do not teach the remaining limitations of claim 7. However, Reed ¶ 0036 teaches an evict fill operation between cache levels wherein an L2 cache evicts data to fill lines in an L1 cache (see ¶ 0037, lines 1-6). If combined with previous disclosures, a cache line may be set to the dirty state by an evict fill, written back, and evicted, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Reed in order to utilize multi-level caches with eviction policies and "mitigate a backlog of L1 data cache evictions in an L2 cache" (¶ 0014, lines 1-5).
As for claim 8, the previously cited references teach the method of claim 7. Additionally, Reed ¶ 0036, lines 10-21 disclose clearing a valid bit associated with a cache line during an evict fill, achieving the claimed limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mulla et al (U.S. Patent No. 5,652,859) discloses techniques for optimizing snooping by distributing requests across buffer queues.
Cantin et al ("Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking) discloses improved techniques for cache coherence in systems similar to those of the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139