Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Status
Present office action is in response to amendment filed 11/19/2025. Claims 2, 6 and 10 are cancelled. Claims 1, 5 and 9 are amended. Claims 1, 3-5, 7-9 and 11-12 are currently pending in the application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-5, 7-9 and 11-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
In regard to independent Claim 1, analyzed as representative claim:
Step 1: Statutory Category?
The preamble of independent Claim 1 recites “a processor implemented method, comprising:”. Independent Claim 1 falls within the “process” category of 35 U.S.C. § 101.
Step 2A – Prong 1: Judicial Exception Recited?
The Revised 2019 Memorandum is applied as shown in the Independent Claim 1/Revised 2019 Guidance Table below to identify in italics the specific claim limitations found to recite an abstract idea and in bold the additional (non-abstract) claim limitations.
Independent Claim 1
Revised 2019 Guidance
A training system for a training of a first user comprising
A method falls under the statutory subject matter class of a process. See
35 U.S.C. § 101 (“Whoever invents or discovers any new and useful
process, machine, manufacture, or composition of matter, or any new and
useful improvement thereof, may obtain a patent therefor, subject to the
conditions and requirements of this title.”).
[L1] obtaining, via one or more hardware processors, a Multi-Stage Testing (MST) block as input, wherein the MST block comprises of a plurality of questions distributed across a plurality of modules; and
Obtaining a Multi-Stage Testing (MST) block as input … is insignificant extra-solution activity (i.e., data gathering). See 2019 Memorandum, 84 Fed. Reg. at 55 n.31; see also MPEP § 2106.05(g).
The one or more hardware processors are generic computer components.
[L2a] calibrating, via the one or more hardware processors, wherein calibrating the MST block uses module-wise calibration comprising a plurality of properties of elementary symmetric functions of change-of-origin property, recurrence relation and grouping property, wherein the change-of-origin property describes effect of a change in origin of item category parameters, wherein for all i and i,:
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where i refers to items and j refers to categories, wherein values ŋ needed to shift the item category parameters of each module onto the common scale is estimated using the module-wise calibration and wherein calibrating the MST block is performed in two stages for striking a balance between scalability and precision, the two stages of calibration comprises;
Calibrating the MST block, comprising: estimating an average difficulty level of each of the plurality of modules is an abstract idea, method of organizing human activity— i.e., managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions and mental process (including an observation, evaluation, judgment, opinion), and mathematical concept. See 2019 Memorandum 52.
The one or more hardware processors are generic computer components.
[L2b] estimating an average difficulty level of each of the plurality of modules;
estimating an average difficulty level of each of the plurality of modules is an abstract idea, method of organizing human activity— i.e., managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions and mental process (including an observation, evaluation, judgment, opinion), and mathematical concept. See 2019 Memorandum 52.
[L2c] estimating difference in the average difficulty level between each two modules from among the plurality of modules, wherein the estimated difference in the average difficulty level is identified as a shift factor ŋ, wherein Conditional Maximum Likelihood (C-L) estimates of the shift factor, ŋ, brings module parameters on a common scale and are determined keeping relative within module difficulties at the estimated values and
Estimating difference in the average difficulty level between each two modules from among the plurality of modules … is an abstract idea, method of organizing human activity— i.e., managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions, mental process (including an observation, evaluation, judgment, opinion) and mathematical concept. See 2019 Memorandum 52.
[L2d] aligning the estimated average difficulty level of each of the plurality of modules to a common scale based on the shift factor wherein the item category parameters across modules are aligned on a common scale using the change-of-origin property, wherein for all items in module k a transformation
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, is used, wherein by aligning the estimated average difficulty level of each of the plurality of modules to the common scale, a plurality of users who took different combinations of the plurality of modules are assessed on the common scale.
Aligning the estimated average difficulty level of each of the plurality of modules to a common scale … is an abstract idea, method of organizing human activity— i.e., managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions and mental process (including an observation, evaluation, judgment, opinion), and mathematical concept. See 2019 Memorandum 52.
The Specification discloses the claimed invention “generally relates to multistage testing, and, more particularly, to method and system for multi-stage testing (MST) calibration” (Spec., ¶ 2). Multi-stage testing is known as a balanced compromise between linear test forms (i.e., paper-and-pencil testing and computer- based testing) and traditional item-level computer-adaptive testing (CAT)1. In multi-stage testing, a test is divided into several stages. This gives the test a few chances to tailor itself for each examinee by selecting an item set that matches the examinee’s ability best for every stage after Stage 1 based on a testee’s responses to previous stages. Adaptive questioning is a method of tailoring the difficulty and type of questions asked based on a candidate's responses, often used in interviews or assessments. For example, in a verbal teacher/student interaction, a teacher could ask a follow-up question based on a response to a previous question, so forth and so on. The claim steps can be accomplished without computers or other external physical tools or devices and is an abstract idea of organizing human activity— i.e., managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions, mental process (including an observation, evaluation, judgment, opinion) and mathematical concept. Thus, other than reciting the additional non-abstract limitations of the one or more hardware processors noted in the Independent Claim 1/Revised 2019 Guidance Table above, nothing in the claim precludes the steps from practically being performed by a human, in the mind, and/or using pen and paper. The mere nominal recitation of the one or more hardware processors does not take the claim out of the method of organizing human activity, mental processes and mathematical concept groupings. It has been held in previous cases that “a mathematical concept need not be expressed in mathematical symbols, because ‘[w]ords used in a claim operating on data to solve a problem can serve the same purpose as a formula.’” MPEP § 2106.04(a)(2), quoting In re Grams, 888 F.2d 835, 837 and n.1 (Fed. Cir. 1989) and citing SAP America, Inc. v. InvestPic, LLC, 898 F.3d 1161, 1163 (Fed. Cir. 2018) (holding that claims to a “series of mathematical calculations based on selected information” are directed to abstract ideas); Digitech Image Techs., LLC v. Elecs. for Imaging, Inc., 758 F.3d 1344, 1350 (Fed. Cir. 2014) (holding that claims to a “process of organizing information through mathematical correlations” are directed to an abstract idea). Accordingly, the claim recites a judicial exception (Step 2A, Prong One: YES).
Step 2A – Prong 2: Integrated into a Practical Application?
The body of the claim, as noted in bold in the Independent Claim 1/Revised 2019 Guidance Table above, recites the additional limitations of the one or more hardware processors which are recited at a high level of generality. The published Specification provides supporting exemplary descriptions of generic computer components: at least ¶ 9: system includes one or more hardware processors, a communication interface, and a memory storing a plurality of instructions; ¶ 13: a non-transitory computer readable medium is provided. The non-transitory computer readable medium includes a plurality of instructions, which when executed, cause one or more hardware processors; ¶ 25: The system 100 includes or is otherwise in communication with hardware processors 102, at least one memory such as a memory 104, an I/O interface 112. The hardware processors 102, memory 104, and the Input/Output (I/O) interface 112 may be coupled by a system bus such as a system bus 108 or a similar mechanism. In an embodiment, the hardware processors 102 can be one or more hardware processors; ¶ 26: The I/O interface 112 may include a variety of software and hardware interfaces, for example, a web interface, a graphical user interface, and the like. The I/O interface 112 may include a variety of software and hardware interfaces, for example, interfaces for peripheral device(s), such as a keyboard, a mouse, an external memory, a printer and the like. Further, the I/O interface 112 may enable the system 100 to communicate with other devices, such as web servers, and external databases; ¶ 28: The one or more hardware processors 102 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, node machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. Among other capabilities, the one or more hardware processors 102 is configured to fetch and execute computer-readable instructions stored in the memory 104; ¶ 30: The plurality of modules 106, amongst other things, can include routines, programs, objects, components, and data structures, which performs particular tasks or implement particular abstract data types. The plurality of modules 106 may also be used as, signal processor(s), node machine(s), logic circuitries, and/or any other device or component that manipulates signals based on operational instructions. Further, the plurality of modules 106 can be used by hardware, by computer-readable instructions executed by the one or more hardware processors 102, or by a combination thereof. The plurality of modules 106 can include various sub-modules (not shown); ¶ 34: the system 100 comprises one or more data storage devices or the memory 104 operatively coupled to the processor(s) 102 and is configured to store instructions for execution of steps of the method 200 by the processor(s) or one or more hardware processors 102; ¶ 77: such computer-readable storage means contain program-code means for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The hardware device can be any kind of device which can be programmed including e.g., any kind of computer like a server or a personal computer, or the like, or any combination thereof. The device may also include means which could be e.g., hardware means like e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of hardware and software means, e.g., an ASIC and an FPGA, or at least one microprocessor and at least one memory with software processing components located therein. Thus, the means can include both hardware means and software means. The method embodiments described herein could be implemented in hardware and software. The device may also include software means. Alternatively, the embodiments may be implemented on different hardware devices, e.g., using a plurality of CPUs; ¶ 78: a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device; ¶ 80: one or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which information or data readable by a processor may be stored. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer-readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., be non-transitory. Examples include random access memory (RAM), read-only memory (ROM), volatile memory, nonvolatile memory, hard drives, CD ROMs, DVDs, flash drives, disks, and any other known physical storage media). The additional elements beyond the abstract idea are the recited one or more hardware processors. The lack of details about the recited additional elements indicates that these additional elements are generic, or part of generic computer elements performing generic computer-implemented steps. The claimed limitations of “obtaining”, “calibrating/estimating”, “estimating”, and “aligning” as recited do not purport to improve the functioning of the one or more hardware processors, do not improve the technology of the technical field, and do not require a “particular machine.” Rather, they are performed using generic computer components. Further, the claim as a whole fails to effect any particular transformation of an article to a different state. The recited steps in the claim fail to provide meaningful limitations to limit the judicial exception. In this case, the claim merely uses the claimed computer elements as a tool to perform the abstract idea.
Considering the elements of the claim both individually and as “an ordered combination” the functions performed by the computer system at each step of the process are purely conventional. Each step performed in the claim does no more than require a generic computer to perform a generic computer function. Thus, the claimed elements have not been shown to integrate the judicial exception into a practical application as set forth in the Revised Guidance which references the Manual of Patent Examining Procedure (“MPEP”) §§ 2106.04(d) and 2106.05(a)–(c) and (e)–(h). Because the abstract idea is not integrated into a practical application, the claim is directed to the judicial exception. (Step 2A, Prong Two: NO).
Step 2B: Claim provides an Inventive Concept?
As discussed with respect to Step 2A Prong Two, the additional elements in the claim amount to no more than mere instructions to apply the exception using generic computer components. The same analysis applies here in Step 2B, i.e., mere instructions to apply an exception using generic computer components cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. Because the Specification, as noted above (¶¶ 9, 13, 25, 26, 28, 30, 34, 77, 78, 80) describes the one or more hardware processors in general terms, without describing the particulars, the claim limitations may be broadly but reasonably construed as reciting conventional computer components and techniques, particularly in light of the published Specification sufficiently well-known that the specification does not need to describe the particulars of such additional elements to satisfy 35 U.S.C. § 112(a). See MPEP 2106.05(d), as modified by the USPTO Berkheimer Memorandum. Furthermore, the Berkheimer Memorandum, Section III (A)(1) explains that a specification that describes additional elements “in a manner that indicates that the additional elements are sufficiently well-known that the specification does not need to describe the particulars of such additional elements to satisfy 35 U.S.C. § 112(a)” can show that the elements are well understood, routine, and conventional); Intellectual Ventures I LLC v. Erie Indem. Co., 850 F.3d 1315, 1331 (Fed. Cir. 2017) (“The claimed mobile interface is so lacking in implementation details that it amounts to merely a generic component (software, hardware, or firmware) that permits the performance of the abstract idea, i.e., to retrieve the user-specific resources.” The generic description of one or more hardware processors indicates the steps are well-known enough that no further description is required for a skilled artisan to understand the process and that these computer components are all used in a manner that is well-understood, routine, and conventional in the field. In particular, the recited data gathering (i.e., [L1] “obtaining a Multi-Stage Testing (MST)” is nothing more than well-understood, routine, and conventional activity because it is not distinguished from the generic, conventional data gathering with a computer. See Elec. Power Grp., 830 F.3d at 1356 (claims to gathering, analyzing, and displaying data in real time using conventional, generic technology do not have an inventive concept). Hence, the additional elements are generic, well-known, and conventional computing elements. The use of the additional elements either alone or in combination amounts to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept, and thus the claims are patent ineligible. (Step 2B: NO).
In regard to independent Claim 5:
Independent claim 5 recites “a system, comprising: one or more hardware processors; a communication interface; and a memory storing a plurality of instructions”, which falls within the “machine” category of 35 U.S.C. § 101. The one or more hardware processors, communication interface and memory additional elements are generic, well-understood, routine, and conventional computing elements (see published Specification ¶¶ 9, 13, 25, 26, 28, 30, 34, 77, 78, 80) for reasons similar to those previously explained when addressing representative independent Claim 1. Additionally, for reasons similar to those previously explained when addressing representative independent Claim 1, under the 2019 Revised Guidance, independent claim 5, considered as a whole, is directed to a patent-ineligible abstract idea that is not integrated into a practical application, and does not include an inventive concept.
In regard to independent Claim 9:
Independent claim 9 recites “one or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause:”, which falls within the “manufacture” category of 35 U.S.C. § 101. The one or more hardware processors additional elements are generic, well-understood, routine, and conventional computing elements (see published Specification ¶¶ 9, 13, 25, 26, 28, 30, 34, 77, 78, 80) for reasons similar to those previously explained when addressing representative independent Claim 1. Additionally, for reasons similar to those previously explained when addressing representative independent Claim 1, under the 2019 Revised Guidance, independent claim 9, considered as a whole, is directed to a patent-ineligible abstract idea that is not integrated into a practical application, and does not include an inventive concept.
In regard to the dependent claims:
Dependent claims 3-4, 7-8 and 11-12 include all the limitations of respective independent claims 1, 5 and 9 from which they depend and, as such, recite the same abstract idea(s) noted above for respective claims 3-4, 7-8 and 11-12. The claims at issue do not require any nonconventional computer, interface, or other components, or even a non-conventional and non-generic arrangement of known, conventional components but merely call for performance of the claimed functions on a set of generic computer components. An invocation to use known technology in the manner it is intended to be used for its ordinary purpose is both generic and conventional. As per MPEP §§ 2106.05(a)–(c), (e)–(h), none of the limitations of claims 3-4, 7-8 and 11-12 integrates the judicial exception into a practical application. While dependent claims 3-4, 7-8 and 11-12 may have a narrower scope than the representative claims, no claim contains an “inventive concept” that transforms the corresponding claim into a patent-eligible application of the otherwise ineligible abstract idea(s). Therefore, dependent claims 3-4, 7-8 and 11-12 are not drawn to patent eligible subject matter as they are directed to (an) abstract idea(s) without significantly more.
Examiner’s Note
No art rejections are currently presented for the claims.
Response to Arguments
Applicant’s arguments regarding the claim rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Claims 1-12 are not directed to an abstract idea:
Step 2A: Claims are not directed to "mental processes", "certain methods of organizing human activity", mathematical concept or "abstract idea."
Applicant essentially argues that “amended claims 1, 5 and 9 are patent-eligible as they implement a judicial exception with or use a judicial exception that effects improvement in the functioning of a computer as discussed in MPEP 2106.04 (d)(1) in terms of computationally stable approach for multi-stage testing (MST) calibration. As the claimed approach does not demand for large assessments, computational efficiency is achieved”. In support of the above, Applicant recites the claim language and further asserts that the “claimed subject matter discloses a module-wise calibration approach for the MST calibration, in which value of a shift parameter is calculated accurately and without the need for large assessments and use of Recurrence relation makes the computations stable and, hence, computational efficiency is achieved” and that the “claimed subject matter cannot be performed in human mind or a mental process, because the claimed steps essentially need computer implemented step or processing through hardware processor”. The Examiner respectfully disagrees.
As noted in the rejections above, the claim steps (1) obtaining a Multi-Stage Testing (MST) block, (2) calibrating the Multi-Stage Testing (MST) block, (3) estimating an average difficulty level of each of the plurality of modules, (4) estimating difference in the average difficulty level between each two modules from among the plurality of modules, (5) and aligning the estimated average difficulty level of each of the plurality of modules to a common scale … involve organizing human activity, mental processes and mathematical calculations. Applicant’s contest of the above stating that the “claimed subject matter cannot be performed in human mind or a mental process, because the claimed steps essentially need computer implemented step or processing through hardware processor” simply indicates using (a) computer component(s) as a tool to perform the abstract idea. As such, the recited “one or more hardware processors” do not integrate the abstract idea into a practical application. See Alice Corp., 573 U.S. at 223–24 (“Wholly generic computer implementation is not generally the sort of ‘additional featur[e]’ that provides any ‘practical assurance that the process is more than a drafting effort designed to monopolize the [abstract idea] itself.”’ (quoting Mayo, 566 U.S. at 77)).
Additionally, Applicant fails to demonstrate that representative claim 1 recites or requires any asserted inventive programming, any specialized computer hardware or other inventive computer components, i.e., a particular machine, or that the claimed invention is performed using other than generic computer components. Nor has Applicant identified any disclosure in the Specification of any inventive techniques or specialized computer components to perform the recited functions of representative claim 1.
Furthermore, Applicant’s disclosure of providing “a method to calculate the elementary symmetric functions of the modules, using a sum-algorithm by Andersen (1972) which was shown to be numerically stable by Verhelst, Glas, and van der Sluijs (1984)”” only further establishes that representative claim 1 recites an abstract idea and is not integrated into a practical application at least because it has been found by the courts that a claim that uses mathematical algorithms to manipulate existing data to generate additional data is not patent eligible. See Digitech Image Techs., LLC v. Elecs. for Imaging, Inc., 758 F.3d 1344, 1351 (Fed. Cir. 2014); Parker v. Flook, 437 U.S. 584, 595 (1978) (explaining that a claim directed to a method of calculating using a mathematical formula is nonstatutory).
Step 2B: Claims recite additional element (s) that amount to significantly more than the judicial exception(s)
Applicant argues that the “claimed subject matter comprises additional elements that amount to a practical application in terms of calibrating and estimating different properties of the various questions given to the examinees while assessing performance of the examinees in Multi- Stage Testing (MST)” and that the “claimed subject matter is computationally stable and undemanding for large assessments and also accurate with significantly less standard errors of estimated item parameters.” Applicant’s arguments are not persuasive. As noted above, the claimed “one or more hardware processors” are generic computer components used in a routine and conventional manner to perform the claim steps. Any improvement set forth by Applicant lies in the abstract realm (i.e., an improvement in the mathematical formula that will use the data obtained by the “one or more hardware processors”). The recitation of “obtaining, via one or more hardware processors, a Multi-Stage Testing (MST) block as input” is insignificant pre-solution activity (i.e., the gathering of data that will be used as input in mathematical calculations) that does not integrate the abstract idea into a practical application and does not add significantly more to the judicial exception.
In light of the foregoing, the Examiner maintains that each of Applicant’s pending claims 1, 3-5, 7-9 and 11-12 considered as a whole, is directed to a patent-ineligible abstract idea that is not integrated into a practical application, and does not include an inventive concept.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EDDY SAINT-VIL/Primary Examiner, Art Unit 3715
1 Zheng et al., Multistage Adaptive Testing for a Large-Scale Classification Test, 2012, ACT Inc.
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