Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 4-7-26 has been entered and fully considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 10, 18 and 19 are rejected under 35 U.S.C. 102a2 as being anticipated by Im et al. (US 2022/0215805).
Regarding claim 1, Im (Fig. 1-3 and 6) discloses a data receiving device comprising:
a first receiver (SW1) configured to receive setting data (EQ_V, called an “equalizer setting value”) for a setting data mode (eg. during T_EQ, as seen in Fig. 6) for setting a display mode at a first data rate through a first communication line (DCSL, “equalizer setting value may be transmitted at a relatively low rate (for example, at a rate of several MHz to hundred MHz) through the data clock signal line DCSL” discussed in [0046]);
a second receiver (313) configured to operate according to setting values included in the setting data (313 “may set a gain and/or a frequency band suitable for a high speed interface based on the equalizer setting value EQ_V” as discussed in [0081]) and receive image data at the display mode (eg. during T_AD, as seen in Fig. 6) at a second data rate different from the first data rate (“image data may be transmitted at a relatively high rate (for example, at a rate of several GHz) through the data clock signal line DCSL” discussed in [0046]) after the setting data mode (as seen in Fig. 6, T_AD is after T_EQ).
Regarding claim 2, Im discloses a data receiving device as discussed above, further comprising:
an image data driver (315) configured to drive pixels of a display panel (pixels PX of display panel 100, 315 “may output the data voltages to data lines Dj to Dm” discussed in [0091] and each pixel “receive a data voltage through a corresponding data line among the data lines D1 to Dm” as discussed in [0042]) according to the image data (315 generates data voltages corresponding to the recovered pieces of image data DATA” discussed in [0091]).
Regarding claim 10, Im discloses a data receiving device as discussed above, further comprising:
a state signal transmitter (as part of 300, transmitting “SBC” as discussed in [0052]) configured to transmit a state signal (SBC) for the first receiver (eg. if “300 is an abnormal state” as discussed in [0052]) through a second communication line (SSL2).
Regarding claim 18, Im (Fig. 1-3 and 6) discloses display device comprising:
a display panel (1000) comprising a plurality of pixels (PX);
a data driver (300) configured to supply data signals to the display panel (via data lines D1-Dm, “provide the data voltages to the data lines D1 to Dm” discussed in [0050]), and
a data processor (200) configured to communicate with the data driver (eg. via DCSL, SSL1, and SSL2),
wherein the data processor (200) is configured to transmit setting data (called an “equalizer setting value”) to a first communication line (DCSL) at a first data rate (“equalizer setting value may be transmitted at a relatively low rate (for example, at a rate of several MHz to hundred MHz) through the data clock signal line DCSL” discussed in [0046]), and
wherein the data driver (300) comprises:
a first receiver (SW1) configured to receive setting data (EQ_V) for a setting data mode (eg. during T_EQ, as seen in Fig. 6) for setting a display mode (“312 may acquire an equalizer setting value EQ_V (or setting value) from the data control signal DCS” discussed in [0077]) at a first data rate through a first communication line (the low rate through DCSL as discussed above, see [0046]); and
a second receiver (313) configured to operate according to setting values included in the setting data (313 “may set a gain and/or a frequency band suitable for a high speed interface based on the equalizer setting value EQ_V” as discussed in [0081]) and receive image data at the display mode (eg. during T_AD, as seen in Fig. 6) at a second data rate different from the first data rate after the setting data mode (“image data may be transmitted at a relatively high rate (for example, at a rate of several GHz) through the data clock signal line DCSL” discussed in [0046]),
wherein the data driver (300) is configured to receive the setting data at the first data rate through the first communication line (eg. from 200 as discussed above, see also “300 may receive the equalizer setting value through the data clock signal line DCSL” as discussed in [0049]), operate according to setting values included in the setting data (“the equalizer setting value may be a value (for example, a code) for setting a gain (or frequency gain) and/or a frequency band of an equalizer” discussed in [0044]), and receive image data at a second data rate different from the first data rate (“image data may be transmitted at a relatively high rate (for example, at a rate of several GHz) through the data clock signal line DCSL” discussed in [0046]).
Regarding claim 19, Im discloses a display device as discussed above, further comprising:
a second communication line (SSL2) through which a state signal (SBC) is transmitted and received (the signal SBC indicates a “normal state” and an “abnormal state” as discussed in [0052]),
wherein the data driver is configured to transmit the state signal to the data processor through the second communication line when an abnormality is detected in the communication (when “the reception state of the data driver 300 is an abnormal state in the third period, the data driver 300 may supply the second control signal SBC having a second value to the timing controller 200 through the second sharing signal line SSL2” as discussed in [0052]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-15 and 21 are rejected under 35 U.S.C. 102a1 as being anticipated by Hong et al. (US 2014/0118235).
Regarding claim 13, Hong (Fig. 1, 2, 4, 7, and 8) discloses a data transmitting device comprising:
a first transmitter (inside TCON, including 12 as seen in Fig. 7) configured to transmit setting data (eg. “control data packet CTRL1 which are stored in the first register 12” as discussed in [0072]) at a setting data mode (eg. CTRL1 is transmit during the first part of CTRL, as seen in Fig. 8, which is part of period HB, seen in Fig. 4) for setting a display mode through a first communication line (seen in Fig. 1, 2, and 7, the TCON is connected to the SDIC through a communication line, with “the control data packet, and a video data packet which are received from the timing controller TCON through data line pairs” in [0048]); and
a second transmitter (another part of the TCON, including both 14 and other elements not shown explicitly in the figures, located to the left of 10 in Fig. 7, providing the “DATA, CLK” signal) configured to transmit image data at the display mode (eg. during period DP, seen in Fig. 4) through the first communication line after the setting data mode (as seen in Fig. 4, after the setting data mode in HB, “RGB Data” corresponding to image data is transmit, called “RGB digital video data” in [0049], see also “TCON sequentially transmits the control data packet and the video data packet to the source driver ICs SDIC#1 to SDIC#8 through the data line pairs DATA&CLK in the order named” discussed in [0058]),
wherein the second transmitter is configured to transmit a control data (eg. using 14) in a blank section (“14 stores start information transmitted in a period (i.e…. the vertical blank period” discussed in [0069]) and transmit the image data in an active section (corresponding to period DP as discussed above).
Regarding claim 21, Hong (Fig. 1, 2, 4, and 7) discloses a data transmitting device configured to transmit setting data (eg. “control data packet CTRL1 which are stored in the first register 12” as discussed in [0072]) at a setting data mode (eg. during period HB, seen in Fig. 4) for setting a display mode through a first communication line (seen in Fig. 1, 2, and 7, the TCON is connected to the SDIC through a communication line, with “the control data packet, and a video data packet which are received from the timing controller TCON through data line pairs” in [0048]) for setting a display mode (eg. to set “control informations which are necessarily used in the operation control of the source driver ICs” during the upcoming display period DP, as discussed in [0061]), and transmit the image data at the display mode (eg. during period DP, seen in Fig. 4) through the first communication line after the setting data mode (as seen in Fig. 4, after the setting data mode in HB, “RGB Data” corresponding to image data is transmit, called “RGB digital video data” in [0049], see also “TCON sequentially transmits the control data packet and the video data packet to the source driver ICs SDIC#1 to SDIC#8 through the data line pairs DATA&CLK in the order named” discussed in [0058]), and transmit a control data in a blank section (eg. using 14, “14 stores start information transmitted in a period (i.e…. the vertical blank period” discussed in [0069]),
wherein the image data is transmitted in an active section (corresponding to period DP).
Regarding claim 14, Hong discloses a data transmitting device as discussed above, further comprising;
an image data processor (part of TCON) configured to process image data for driving pixels of a display panel (eg. processing the image data by combining it with other information for transmitting to the SDIC, see “video data packet is a bit stream including clock bit, internal data enable bit, RGB data bit, etc.” discussed in [0052]).
Regarding claim 15, Hong discloses a data transmitting device as discussed above, wherein the second transmitter is configured to transmit the image data and first control data in a first section of a frame time (as seen in Fig. 4, a first section of each frame, corresponding to one line, includes a horizontal blank period HB and corresponding display period DP, and includes both control data “CTRL” and image data “RGB Data,” see also “horizontal blank period HB is a very short period of time, in which there is no data, between an Nth horizontal period and an (N+1)th horizontal period” discussed in [0059]) and second control data in a second section of the frame time (the “control data packet is transmitted in a… vertical blank period” as discussed in [0059]), and
wherein the first control data includes a control value applied in a line unit or a pixel unit of the display panel (“control data packet transmitted in the horizontal blank period HB may include only necessary control informations, for example, source output enable signal related information and polarity control signal related information, which are necessarily used in the operation control of the source driver ICs SDIC#1 to SDIC#8 and have to be transmitted in each horizontal period” as discussed in [0061], eg. only control data for the current line) and the second control data includes a control value applied in a period longer than the line unit or a control value applied in a frame unit (the control data in the vertical blank period includes settings for the entire frame, such as “gamma compensation control informations,” see “control data packet… may include the necessary control informations and the selection option control informations,” discussed in [0062]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 1 above, and further in view of Zheng et al. (US 2020/0042264).
Regarding claim 3, Im discloses a data receiving device as discussed above, wherein the second receiver includes a clock recovery circuit (314),
wherein the clock recovery circuit restores a high-speed communication clock from an embedded clock signal received at the second data rate (“recover a clock signal CLK” discussed in [0089]),
wherein the second circuit extracts the image data from the embedded clock signal according to the high-speed communication clock (“recover the pieces of the image data DATA from the output signal C_DCS of the equalizer 313 in synchronization with the clock signal CLK” discussed in [0089]).
However, Im still fails to teach or suggest “wherein the setting data includes a setting value of the clock recovery circuit.”
Zheng (Fig. 2) discloses a data receiving device wherein setting data (called “configuration bits” in [0063]) includes a setting value of the clock recovery circuit (seen in Table 1 after paragraph [0063], the configuration bits includes “CDR control” bits which “Control the CDR bandwidth, charge pump current,” with “receiver clock data recovery (CDR)” discussed in more detail in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im so the setting data includes a setting value of the clock recovery circuit as taught by Zheng because this allows the clock recovery circuit to be adjusted to calibrate it or compensate for errors.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Im and Zheng as applied to claim 3 above, and further in view of Yoo et al. (US 2017/0111071).
Regarding claim 4, Im and Zheng disclose a data receiving device as discussed above, however fail to teach or suggest wherein the second receiver includes a deserializer configured to parallelize the image data extracted from the embedded clock signal in a byte unit or a symbol unit.
Yoo (Fig. 3 and 14) discloses a data receiving device wherein a receiver (121) includes a deserializer (126) configured to parallelize (“deserializer 126 may convert serial data into parallel data” discussed in [0070]) the image data (“among received data, image data may be provided” discussed in [0142]) extracted from the embedded clock signal (“126 may convert serial data into parallel data based on a clock signal that is provided from the CDR circuit 125” discussed in [0070]) in a byte unit or a symbol unit (eg. a symbol unit corresponding to one “row” of pixels, see “image data corresponding to pixels of one row of a display panel (for example, the display panel 230 of FIG. 11) is stored in the data latch unit 224” discussed in [0142]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im and Zheng to include a deserializer configured to parallelize the image data extracted from the embedded clock signal in a byte unit or a symbol unit as taught by Yoo because this allows parallel image data to be supplied to a A/D converting unit to select a gradation voltage (see [0142]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Im, Zheng, and Yoo as applied to claim 4 above, and further in view of Iwami (US 2017/0154597) and Lund (US 2010/0310067).
Regarding claim 5, Im, Zheng, and Yoo disclose a data receiving device as discussed above, however fails to teach or suggest wherein the second receiver includes a decoder configured to decode the image data, encoded by using a DC balance code or a limited run length code (LRLC), based on a decoding table stored in a memory.
Iwami (Fig. 6) discloses a data receiving device wherein a receiver (20) includes a decoder (207) configured to decode the image data (similar to “decode the image data Dp3” discussed in [0048]), encoded by using a DC balance code (eg. “8b/10b” encoding as discussed in [0056], which is a DC balance code) or a limited run length code (LRLC) (this limitation is not being examined due to the alternative language “or”), based on a decoding table (similar to “decoder 203 decodes with the use of the third conversion table” discussed in [0048], see [0056] which discusses how 203 is replaced with 207 to use 8b/10b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im, Zheng, and Yoo so the second receiver includes a decoder configured to decode the image data, encoded by using a DC balance code or a limited run length code (LRLC), based on a decoding table as taught by Iwami because this reduces the processing required for decoding compared to calculation, while also allowing conversions that do not strictly follow mathematical formulas.
However, Im, Zheng, Yoo, and Iwami still fail to teach or suggest a “decoding table stored in a memory.”
Lund discloses wherein 8B10B encoding (“8B10B encoding table” discussed in [0057]) can be decoded using a decoding table stored in a memory (“decoding tables may be stored, for example, in ROM, RAM, or flash memory as lookup tables” discussed in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im, Zheng, Yoo, and Iwami so the decoding table is stored in a memory as taught by Lund because storing in non-volatile memory (like ROM) allows the values to be saved even after power loss, preventing the additional overhead required to recalculate the decoding table.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Im, Zheng, Yoo, Iwami, and Lund as applied to claim 5 above, and further in view of Kim et al. (US 2020/0126508, hereafter “Kim ‘508”).
Regarding claim 6, Im, Zheng, Yoo, Iwami, and Lund disclose a data receiving device as discussed above, however fail to teach or suggest a descrambler.
Kim ‘508 (Fig. 3) discloses a data receiving device wherein a communication circuit (224) includes a descrambler (322) configured to restore the image data (“312 scrambles data, for example, image data” discussed in [0055]), scrambled according to a prescribed protocol (“scrambling is performed according to a previously agreed protocol” as discussed in [0055]), to data in an original state (“descrambler 322 may perform a function of restoring a stream in which bits are shuffled to original data” discussed in [0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im, Zheng, Yoo, Iwami, and Lund so the second communication circuit includes a descrambler configured to restore the image data, scrambled according to a prescribed protocol, to data in an original state as taught by Kim ‘508 because this allows scrambled data to be transmitted without excessive consecutive symbols, reducing errors, while still allowing the original data to be restored.
Regarding claim 7, Im, Zheng, Yoo, Iwami, and Lund disclose a data receiving device as discussed above, however fail to teach or suggest wherein the second receiver includes an unpacker.
Kim ‘508 (Fig. 3) discloses a data receiving device wherein a receiver includes an unpacker (321) configured to align the image data in pixel unit (“321 may align the data in bytes and in pixels” discussed in [0064]) and transmit the aligned image data to the data receiving circuit (transmit out of the top of 321 as “image data” as seen in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im, Zheng, Yoo, Iwami, and Lund so the second receiver includes an unpacker configured to align the image data as taught by Kim ‘508 because this allows data from the pixels to be read (see [0066]) and prevents data from different pixel from interfering with each other.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 1 above, and further in view of Kim ‘508.
Regarding claim 8, Im discloses a data receiving device as discussed above, and although Im further discloses wherein the first receiver includes a decoder (530), Im fails to teach or suggest wherein a first receiver includes a deserializer configured to parallelize a communication signal received in a serial form through the first communication line and decode the communication signal by using a Manchester code.
Kim ‘508 (Fig. 3) discloses a data receiving device wherein a first receiver (224) includes a deserializer (326) configured to parallelize a communication signal (“Serial-to-parallel conversion of data may be performed by the P2S converting unit 316” discussed in [0060]) received in a serial form through the first communication line (LN1) and decode the communication signal (using 324) by using a Manchester code (“data bits may be encoded using a Manchester-II code” discussed in [0123]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im to include a deserializer as taught by Kim ‘508 because this allows the data to be transmit in “serial form” to reduce the number of wires required, and deserializing the data allows it to be converted back into parallel data, which can be processed more quickly than serial data.
Regarding claim 9, Im and Kim ‘508 disclose a data receiving device as discussed above, and Kim ‘508 further discloses wherein the communication signal (seen in Fig. 9) comprises:
a first part including a low-speed communication clock (“a clock may be transmitted through a first part P1” discussed in [0123]),
a second part including a start signal (“a start signal” as discussed in [0125]),
a third part including a message header (“message header may be transmitted via a third part P3” as discussed in [0126]),
a fourth part including the setting data (“fourth part P4 may include information transmitted and received through the message” as discussed in [0127]),
a fifth part including an error check value (“fifth part P5 may include a checksum” as discussed in [0128]), and
a sixth part including an end signal (“end signal indicating the end of the message is transmitted via a sixth part P6” as discussed in [0125]).
It would have been obvious to one of ordinary skill in the art to combine Im and Kim ‘508 for the same reasons as discussed above.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 10 above, and further in view of Kim et al. (US 2022/0028320, hereafter “Kim ‘320”).
Regarding claim 11, Im discloses a data receiving device as discussed above, however fails to teach or suggest a performance evaluator.
Kim ‘320 (Fig. 5) discloses a data receiving device including a performance evaluator configured to transmit a performance evaluation feedback signal (“data processing device may transmit the first pattern signal TRP1 to the data driving device” discussed in [0107]) for a communication evaluation result (“evaluate the reception performance of the signal transmitted by the data processing device according to the bit error rate” as discussed in [0107]) obtained based on a recognition rate of a test pattern (TRP1) received through the first communication line (TRP1 is transmit along LN1 as discussed in [0141]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im to include a performance evaluator as taught by Kim ‘320 because this allows detection of reception problems and allows for “improving the quality of the signal” (see [0107]).
Regarding claim 12, Im and Kim ‘320 disclose a data receiving device as discussed above, and Kim ‘320 further discloses the device comprising:
a signal combiner configured to combine the state signal with the performance evaluation feedback signal (“when the first pattern signal TRP1 is not detected… transmit a lock signal indicating unlocking to the data processing device (LOCK=L)” as discussed in [0176]) and transmit a combined signal (eg. corresponding to either the result from the performance evaluation or an indication from the lock controlling circuit 840 that the data driving device is in an abnormal state, see [0138]) to the second communication line (“signal ALP may be referred to as a LOCK signal” and is transmit across LN2 as discussed in [0080]).
It would have been obvious to one of ordinary skill in the art to combine Im and Kim ‘320 for the same reasons as discussed above.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 13 above, and further in view of Kim ‘508.
Regarding claim 16, Hong discloses a data transmitting device as discussed above, further comprising a packer (part of 10, not shown explicitly in the figures) configured to generate transmission data (on the DATA&CLK line) by packaging at least one of the image data (eg. “RGB bits of the video data packet” discussed in [0049]), the first control data (eg. the “CTRL” packet, shown packaged together on the same EPI transmission lines in Fig. 3), and the second control data (this limitation is not being examined due to the alternative language “at least one of”).
However, Hong fails to teach or suggest a scrambler, encoder, or serializer.
Kim ‘508 (Fig. 3) discloses a data transmitting device wherein a transmitter (244) includes:
a scrambler (312) configured to scramble some or all of the transmitted data (“312 scrambles data” discussed in [0055]);
an encoder (314) configured to encode the transmission data by using a DC balance code (“encoding method with a DC balance code” discussed in [0056]) or a limited run length code (LRLC) (this limitation is not being examined due to the alternative language “or”); and
a serializer (316) configured to convert the transmission data in a serial form to form a transmission stream (“Serial-to-parallel conversion of data may be performed by the P2S converting unit 316” discussed in [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hong to include a scrambler, encoder, and serializer as taught by Kim ‘508 because this allows data transmission with fewer lines compared to parallel transmission.
Regarding claim 17, Hong and Kim ‘508 disclose a data transmitting device as discussed above, and Kim ‘508 further discloses wherein the serializer is configured to distribute the transmission data to each of two or more pairs to transmit the distributed transmission data (“a plurality of first communication lines LN1 is used” and “each first communication line LN1 may include two signal lines” discussed in [0053]).
It would have been obvious to one of ordinary skill in the art to combine Hong and Kim ‘508 for the same reasons as discussed above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 19 above, and further in view of Hong.
Regarding claim 20, Im discloses a display device as discussed above, wherein:
the data driver includes a plurality of data drivers (as seen in Fig. 2, 300 includes multiple data drivers 310),
the first communication line is configured to connect the data processor and each of the data drivers in a one-to-one way (as seen in Fig. 2, each 310 connects to 200 through a separate line DCSL, see also “each of the data clock signal lines may be a one-way transmission line from the timing controller to each of the data driving circuits” discussed in [0009]).
However, Im fails to teach wherein the second communication line is configured to connect the data processor and the data drivers in a cascade form.
Hong (Fig. 1 and 2) discloses a display device wherein:
a data driver (including each SDIC) includes a plurality of data drivers (as seen in Fig. 2, including multiple data drivers SDIC#1-SDIC#8),
a first communication line (called “DATA&CLK” in Fig. 2) is configured to connect the data processor and each of the data drivers in a one-to-one way (as seen in Fig. 2, each SDIC connects to TCON through a separate line, see also “data line pairs DATA&CLK connect the timing controller TCON in series to the source driver ICs SDIC#1 to SDIC#8 in one-to-one manner” discussed in [0052]),
a second communication line (shown as a dotted line in Fig. 2, connecting each SDIC on the bottom, and labelled LCS2 on the right) through which a state signal (called a “lock signal LOCK” in [0053], and “indicating an output stabilization state” as discussed in [0014]) is transmitted and received (“transmits the lock signal LOCK of the high logic level to the timing controller TCON through a feedback lock check line LCS2” discussed in [0053]),
wherein the second communication line (the dotted line seen in Fig. 2, as discussed above) is configured to connect the data processor and the data drivers in a cascade form (seen in Fig. 2, see also “source driver ICs SDIC#1 to SDIC#8 may be cascade-connected to one another through lines (indicated by dotted lines of FIG. 2) used to transmit the lock signal LOCK” discussed in [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Im so the second communication line is configured to connect the data processor and the data drivers in a cascade form as taught by Hong because this allows the timing controller to confirm “that the outputs of the clock recovery circuits of the source driver ICs SDIC#1 to SDIC#8 are stably locked” (see [0053]).
Response to Arguments
Applicant's arguments filed 3-23-26 have been fully considered but they are not persuasive.
First, regarding claim 1, due to the amendements, the rejection has been modified to rely on the reference of Im, instead of Kim ‘339.
Regarding claims 13 and 21, the applicant argues that Hong fails to teach or suggest the second transmitted configured to transmit control data in a blank section and image data in an active section. The examiner respectfully disagrees. As discussed in the modified rejection above, the “second transmitter” of Hong includes both the sources of the DATA,CLK signal seen in Fig. 7, but also element 14, which stores and transmits control data. Further, the second transmitter is configured to transmit the control data in a blank section (eg. called a “vertical blank period,” see “14 stores start information transmitted in a period (i.e…. the vertical blank period” discussed in [0069]) and transmit the image data in an active section (period DP is not a “blank” section and so the examiner is interpreting period DP to read upon the claimed “active section”).
Regarding claim 18, the applicant argues that Im fails to teach or suggest a “distinct” first receiver or second receiver. The examiner respectfully disagrees. The claims are broad, and do not particularly limit the structure or connections of the “receivers,” and so the examine interprets the separate and distinct elements SW1 and 313 to read on the claimed “first receiver” and “second receiver,” respectively. More specifically, as discussed above, SW1 properly “receives” the EQ_V signal that is transmit through DCSL as part of the DCS signal, and then passes the received signal to the top of 313 as seen in Fig. 3A. Similarly, 313 properly “receives” data signals that are transmit through DCSL as part of the DCS signal (via SW2, see “SW2 may transmit the data control signal DCS to the equalizer 313 as a clock training signal and pieces of image data” discussed in [0082]).
The applicant also argues that Im fails to teach or suggest a “setting data mode” that occurs prior to a “display mode.” More specifically, the applicant argues that “the first and second periods are included within a vertical blank period,” and the “vertical blank period is a component of the display mode itself.” The examiner respectfully disagrees. Again, the claims are broad and do not specifically define the “setting data mode” or the “display mode.” As discussed above, the EQ_V signal is sent to the first receiver SW1 during a first period (eg. corresponding to T_EQ in Fig. 6), which the examiner is interpreting as a “setting data mode,” and the image data is sent to the second receiver 313 via SW2 during a second period (eg. corresponding to T_AD in Fig. 6), which the examiner is interpreting as a “display mode.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN M BLANCHA whose telephone number is (571)270-5890. The examiner can normally be reached Monday to Friday, 9-5.
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/JONATHAN M BLANCHA/ Primary Examiner, Art Unit 2623
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