CTNF 18/966,557 CTNF 77802 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-36-01 Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. As stated in [0005-0006] and [0013-0016] of the present application specification, Figs. 1-2 are conventional and thus are considered prior art. Claim Objections 07-29-01 AIA Claim 1 is objected to because of the following informalities: In Claim 1 (lines 8-15), it appears the phrase: “a first end conductively coupled to the end of the of the first linear conductive trace; and a second end; and a second curved conductive trace formed in the first metal layer, and including: a first end conductively coupled to the second end of the first curved conductive trace; and a second end conductively coupled to the end of the second linear conductive trace.” should instead read as: --a first end conductively coupled to the end of the of the second linear conductive trace; and a second end; and a second curved conductive trace formed in the first metal layer, and including: a first end conductively coupled to the second end of the first curved conductive trace; and a second end conductively coupled to the end of the first linear conductive trace.-- since the first end (e.g. 316B) of the first curved trace (316) is connected to the second linear trace (306) rather than the first linear trace (304) which is consistent with the specification since 304 is described as having an end coupled to the coupled port . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim s 9-10, 13, and 15 are rejected under 35 U.S.C. 102 a1 as being clearly anticipated by Srirattana et al. (US 2017/0317395 cited by applicant) . Srirattana (e.g. Fig. 3E) teaches a directional coupler including: Regarding Claim 9, An on-chip directional coupler (e.g. see [0055]), comprising: a first linear conductive trace including an end and a coupled port (e.g. 106); a second linear conductive trace, spaced apart from and parallel to the first linear conductive trace (e.g. 112 is linear and parallel between the ports 106, 108 and loop), and including an end and an isolated port (e.g. 108); and a conductive loop including: a first end conductively coupled to the end of the first linear conductive trace; and a second end conductively coupled to the end of the second linear conductive trace (e.g. the loop 112 has its ends connected to the two linear parallel portions that are connected to the ports 106, 108). Regarding Claim 10, wherein the first linear conductive trace and the second linear conductive trace are formed in a first metal layer (e.g. the linear conductors are may be on one layer see [0055]). Regarding Claim 13, further comprising: a signal trace (main line 110) disposed around the first linear conductive trace, the second linear conductive trace, and the conductive loop; the signal trace including an input port (102) and an output port (104) (e.g. the main line is around the perimeter of the rest of the device). Regarding Claims 15, wherein: magnetic coupling in the on-chip directional coupler is a function of a ratio of diameter of the conductive loop to length of the first linear conductive trace and the second linear conductive trace; and diameter of the conductive loop is measured along a centerline of the conductive loop that is parallel to the first linear conductive trace and the second linear conductive trace(e.g. the claim is merely describing the functionality of the structural details and the Srirattana device includes the same structural details as the present invention claim which thus would function the same) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Srirattana et al. (US 2017/0317395 cited by applicant) in view of Applicant’s Admitted Prior Art (AAPA) . Srirattana teaches a coupler as described above. However, Srirattana does not appear to teach a plurality of linear conductive trace segments configured to periodically load the signal trace. The AAPA (e.g. Fig. 1 of the present application and [0015-0016] of the present specification) provide the conventional/prior art teachings of a plurality of linear conductive trace segments configured to periodically load the signal trace. It would have been considered obvious to one of ordinary skill in the art to have modified the Srirattana coupler to have included a plurality of linear conductive trace segments configured to periodically load the signal trace such as taught by the AAPA, because the addition of loading traces would have provided the advantageous benefit of helping control parasitic capacitance such as taught by the AAPA . 07-21-aia AIA Claim s 1-13, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kusuno et al. (JP 2008244924A cited by applicant) in view of Matsumoto et al. (US 2020/0212529) . Kusuno teaches (e.g. Figs. 1-7) a directional coupler including: PNG media_image1.png 557 669 media_image1.png Greyscale Regarding Claim 1, (see the annotated Figure above), a first linear conductive trace in a first metal layer, and including an end and a coupled port (e.g. for a detection device, see [0072) ; a second linear conductive trace, spaced apart from and parallel to the first linear conductive trace, in the first metal layer, and including an end and an isolated port (e.g. the port of 12b is connected to an isolating resistor 5, see [0084]); a first curved conductive trace in a second metal layer (e.g. see Figs. 3 and 5, showing the second metal layer having conductors such as 13b), and including: a first end conductively coupled to the end of the second linear conductive trace (e.g. the end of the curved conductor conductively connects back to the 1 st via which is connected to the end of the 2 nd linear trace 12b); and a second end; and a second curved conductive trace in the first metal layer (e.g. the curved portions of 13a are on the first layer as shown in Figs. 3 and 5), and including: a first end conductively coupled to the second end of the first curved conductive trace (e.g. the end of the conductor 13a is conductively coupled to 2 nd via 15 that is closest to the 1 st linear trace and that via is connected to the 1st curved conductor that is on the second metal layer); and a second end conductively coupled to the end of the first linear conductive trace ( e.g. see annotated figure, “End of 1 st trace”). Regarding Claim 2, further comprising: a first via connecting the end of the second linear conductive trace and the first end of the first curved conductive trace (e.g. see 1st via in annotations, the via conductively connects between the 2 nd linear trace and the 1 st curved conductor); and a second via connecting the second end of the first curved conductive trace and the first end of the second curved conductive trace (e.g. see 2 nd via in annotations, which conductively connects the curved conductors located on the first and second metal layers). Regarding Claim 3, further comprising: a signal trace (e.g. 11) around the first linear conductive trace, the second linear conductive trace, the first curved conductive trace, and the second curved conductive trace, the signal trace including an input port and an output port (e.g. Fig. 1 shows signal trace 11 can be around the perimeter of the other/secondary portions of the coupler). Regarding Claim 4, wherein the signal trace is in the second metal layer (e.g. Figs. 5-6 show the option to have the signal trace 11 of the second layer). Regarding Claims 5 and 18, further comprising: a plurality of linear conductive trace segments; wherein each of the conductive trace segments is: orthogonal to the signal trace; and on a different metal layer than the signal trace (e.g. see the annotate figure above which shows linear segments orthogonal to 11 and on a different layer). Regarding Claim 6, the first curved conductive trace includes a first conductive trace segment (e.g. the portion of 13b having the arrow in the annotated figure above) perpendicular to the first linear conductive trace and the second linear conductive trace; and the second curved conductive trace includes a second conductive trace segment perpendicular to the first linear conductive trace and the second linear conductive trace (e.g. the portion of 13a having the arrow in the annotated figure above). Regarding Claim 7, the second curved conductive trace includes a third conductive trace segment conductively coupled to and perpendicular to the second conductive trace segment (e.g. the short portion of 13a that appears to overlap 13c is perpendicular to the second segment of claim 6). Regarding Claim 8, wherein the second curved conductive trace includes a fourth conductive trace segment (e.g. the straight portion of 13a that directly connects to the 2 nd via) conductively coupled to and perpendicular to the third conductive trace segment. Regarding Claims 9 and 11-12, a first linear conductive trace including an end and a coupled port; a second linear conductive trace, spaced apart from and parallel to the first linear conductive trace, and including an end and an isolated port; (e.g. see Claim 1 above for the same details); and a conductive loop having a first curved conductive trace and a second curved conductive trace, the conductive loop including: a first end of the first curved conductive trace conductively coupled to the end of the second linear conductive trace through the first via; a second end of the first curved conductive trace conductively coupled to a first end of the second curved conductive trace through the second via; and a second end of the second curved conductive trace coupled to the end of the first linear conductive trace (e.g. the first and second curved portions as described regarding Claim 1 above, and as shown in the annotated figure above, curving portions 13a, 13b ,13c form generally a looping shape including the vias). Regarding Claim 10, wherein the first linear conductive trace and the second linear conductive trace are in a first metal layer (e.g. see regarding Claim 1 above). Regarding Claims 13 and 17, further comprising: a signal trace around the first linear conductive trace, the second linear conductive trace, and the conductive loop; and the signal trace including an input port and an output port (e.g. see regarding Claims 3 and 9 above). Regarding Claims 15 and 20, magnetic coupling in the directional coupler is a function of a ratio of diameter of the conductive loop to length of the first linear conductive trace and the second linear conductive trace; and diameter of the conductive loop is measured along a centerline of the conductive loop that is parallel to the first linear conductive trace and the second linear conductive trace (e.g. the claim is merely describing the functionality of the structural details and the Kusuno device includes the same structural details as the present invention claim which thus would function the same). Regarding Claim 16, Kusuno teaches all of the details of the coupler as detailed regarding Claims 1 and 9 above including the detection circuit (i.e. for detecting signals) at 12a, and also Fig. 2 of Kusuno shows a power amplifier (e.g. 22) in an integrated circuit connected to the coupler at one end of transmission conductor (2) and the conductor has its other end connected to the signal trace (11) of the coupler (i.e. at a transmit terminal). However, regarding Claims 1, 9, and 16 Kusuno does not appear to teach that the directional coupler can be on a chip/integrated. Matsumoto provides the general teaching to put directional couplers on integrated chips (e.g. see [0006]). It would have been considered obvious to one of ordinary skill in the art to have modified the Kusuno coupler to have been on an integrated chip such as taught by Matsumoto, because it would have provided the advantageous benefits of integration with other components and miniaturization such as taught by Matsumoto (see [0006]), thereby suggesting the obviousness of the modification . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kusuno et al. (JP 2008244924A cited by applicant) in view of Matsumoto (US 2020/0212529) . The combination of Kusuno and Matsumoto teaches a directional coupler as described above. However, Kusuno does not appear to explicitly teach that the first linear conductive trace is configured to provide current flow to the conductive loop; and the second linear conductive trace is configured to provide current flow from the conductive loop. It would have been considered obvious and routine to one of ordinary skill in the art to have modified the Kusuno device to have the secondary conductor ports reversed such that the first linear conductive trace is configured to provide current flow to the conductive loop; and the second linear conductive trace is configured to provide current flow from the conductive loop, especially since directional couplers are reciprocal devices that allow for signaling and current flow to be capable of propagating in either direction and thus the modification of current flow direction would have been a mere selection of component orientation/locating at the directional coupler’s secondary ports without having an effect on the coupling functionality . 07-22-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kusuno et al. (JP 2008244924A cited by applicant) and Matsumoto et al. (US 2020/0212529) as applied to claim s 9 and 13 above, and further in view of Applicant’s Admitted Prior Art (AAPA) . Kusuno teaches a coupler as described above. However, Kusuno does not appear to teach a plurality of linear conductive trace segments configured to periodically load the signal trace. The AAPA (e.g. Fig. 1 of the present application and [0015] of the present specification) provide the conventional/prior art teachings of a plurality of linear conductive trace segments configured to periodically load the signal trace. It would have been considered obvious to one of ordinary skill in the art to have modified the combination of Kusuno/Matsumoto coupler to have included a plurality of linear conductive trace segments configured to periodically load the signal trace such as taught by the AAPA, because the addition of loading traces would have provided the advantageous benefit of helping control parasitic capacitance such as taught by the AAPA . Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto- processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim s 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-11, 13-16, and 18-26 of copending Application No. 17/349,022 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application claims teach all of the same elements as the present claims either in the same terms or in different terms resulting in the same structure but the reference application claims are more comprehensive/narrow, but the reference application claims do not teach that the directional coupler is integrated in a chip. Matsumoto provides the general teaching to put directional couplers on integrated chips (e.g. see [0006]). It would have been considered obvious to one of ordinary skill in the art to have modified the reference application claims device/coupler to have been on an integrated chip such as taught by Matsumoto, because it would have provided the advantageous benefits of integration with other components and miniaturization such as taught by Matsumoto (see [0006]), thereby suggesting the obviousness of the modification . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN E JONES whose telephone number is (571)272-1762. The examiner can normally be reached 9AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Stephen E. Jones/Primary Examiner, Art Unit 2843 Application/Control Number: 18/966,557 Page 2 Art Unit: 2843 Application/Control Number: 18/966,557 Page 3 Art Unit: 2843 Application/Control Number: 18/966,557 Page 4 Art Unit: 2843 Application/Control Number: 18/966,557 Page 5 Art Unit: 2843 Application/Control Number: 18/966,557 Page 6 Art Unit: 2843 Application/Control Number: 18/966,557 Page 7 Art Unit: 2843 Application/Control Number: 18/966,557 Page 8 Art Unit: 2843 Application/Control Number: 18/966,557 Page 9 Art Unit: 2843 Application/Control Number: 18/966,557 Page 10 Art Unit: 2843 Application/Control Number: 18/966,557 Page 11 Art Unit: 2843 Application/Control Number: 18/966,557 Page 12 Art Unit: 2843 Application/Control Number: 18/966,557 Page 13 Art Unit: 2843 Application/Control Number: 18/966,557 Page 14 Art Unit: 2843 Application/Control Number: 18/966,557 Page 15 Art Unit: 2843 Application/Control Number: 18/966,557 Page 16 Art Unit: 2843
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