DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 9/19/2025 and 9/08/2026 have been entered and considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11330614. Although the claims at issue are not identical, they are not patentably distinct from each other. Please see the direct claim comparison below.
Instant Application Claim 1
11330614 Claim 1
An integrated circuit, which comprises circuitry configured to:
A user equipment for transmitting and/or receiving data to/from a base station using multiple antennas in a communication system, the user equipment comprising:
control receiving, at a user equipment, a parameter defining a configuration for assigning to ports resources for carrying reference signals;
control receiving, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
a receiver, which, in operation,
receives a parameter defining a configuration for assigning to ports respective resources for carrying reference signals, and
receives, from the base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
control the data transmission and/or reception based on the indicated layer-to-port mapping combination;
circuitry, which, in operation, performs the data transmission and/or reception based on the indicated layer-to-port mapping combination,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include a mapping combination having consecutive port numbers of which at least one port number is duplicated in another mapping combination for the same n layers which is continuously indexed.
As can be seen from the direct claim comparison above, instant application claim 1 is merely a variation of US Patent 11330614 and all limitations from instant application claim 1 are clearly disclosed in US Patent 11330614. Therefore, this is clearly an obvious type non-statutory double patenting issue.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 11716722. Although the claims at issue are not identical, they are not patentably distinct from each other. Please see the direct claim comparison below.
Instant Application Claim 1
11716722 Claim 1
An integrated circuit, which comprises circuitry configured to:
An integrated circuit for controlling a user equipment, the integrated circuit comprising:
control receiving, at a user equipment, a parameter defining a configuration for assigning to ports resources for carrying reference signals;
control receiving, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
receiving circuitry, which, in operation,
receives a parameter defining a configuration for assigning to ports respective resources for carrying reference signals, and
receives, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
control the data transmission and/or reception based on the indicated layer-to-port mapping combination;
control circuitry, which, in operation, performs the data transmission and/or reception based on the indicated layer-to-port mapping combination,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include a mapping combination having consecutive port numbers of which at least one port number is duplicated in another mapping combination for the same n layers which is continuously indexed.
As can be seen from the direct claim comparison above, instant application claim 1 is merely a variation of US Patent 11716722 and all limitations from instant application claim 1 are clearly disclosed in US Patent 11716722. Therefore, this is clearly an obvious type non-statutory double patenting issue.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 11937237. Although the claims at issue are not identical, they are not patentably distinct from each other. Please see the direct claim comparison below.
Instant Application Claim 1
11937237 Claim 1
An integrated circuit, which comprises circuitry configured to:
An integrated circuit for controlling a base station for receiving and/or transmitting data from/to a user equipment in a communication system, the integrated circuit comprising:
control receiving, at a user equipment, a parameter defining a configuration for assigning to ports resources for carrying reference signals;
control receiving, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
transmitting circuitry, which, in operation, transmits a parameter defining a configuration for assigning to ports
respective resources for carrying reference signals, and transmits, to the user equipment, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data reception and/or transmission; and
control the data transmission and/or reception based on the indicated layer-to-port mapping combination;
control circuitry, which, in operation, performs the data transmission and/or reception based on the indicated layer-to-port mapping combination,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein first indices of the continuous indices indicate the one-symbol layer-to -port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer -to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
As can be seen from the direct claim comparison above, instant application claim 1 is merely a variation of US Patent 11937237 and all limitations from instant application claim 1 are clearly disclosed in US Patent 11937237. Therefore, this is clearly an obvious type non-statutory double patenting issue.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 12192998. Although the claims at issue are not identical, they are not patentably distinct from each other. Please see the direct claim comparison below.
Instant Application Claim 1
12192998 Claim 1
An integrated circuit, which comprises circuitry configured to:
A user equipment comprising:
control receiving, at a user equipment, a parameter defining a configuration for assigning to ports resources for carrying reference signals;
control receiving, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
a receiver, which, in operation,
receives a parameter defining a configuration for assigning to ports respective resources for carrying reference signals, and
receives, from a base station, control information indicating one of a set of layer-to-port mapping combinations which is to be applied for data transmission and/or reception; and
control the data transmission and/or reception based on the indicated layer-to-port mapping combination;
circuitry, which, in operation, performs the data transmission and/or reception based on the indicated layer-to-port mapping combination;
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein the resources carrying the reference signals are located on one or more symbols in a time domain, wherein the set of layer-to-port mapping combinations are continuously indexed including one-symbol layer-to-port mapping combinations for the reference signals located on one symbol and two-symbol layer-to-port mapping combinations for the reference signals located on two symbols,
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein first indices of the continuous indices indicate the one-symbol layer-to-port mapping combinations followed by second indices for the two-symbol layer-to-port mapping combinations, and
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
wherein, of the set of layer-to-port mapping combinations, the two-symbol layer-to-port mapping combinations for n layers (where n is 2 or more) include first mapping combinations and a second mapping combination which is continuously indexed next to the first mapping combinations, the first mapping combinations having consecutive port numbers of which at least one port number is duplicated in the second mapping combination.
As can be seen from the direct claim comparison above, instant application claim 1 is merely a variation of US Patent 12192998 and all limitations from instant application claim 1 are clearly disclosed in US Patent 12192998. Therefore, this is clearly an obvious type non-statutory double patenting issue.
Allowable Subject Matter
Claims 1-20 are allowable except for the Double Patenting rejections, as shown above. It is suggested that Applicant file a eTerminal Disclaimer so that a Notice of Allowance may be issue.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENT KRUEGER whose telephone number is (303)297-4238. The examiner can normally be reached on M-F 8:00-5:00 MT.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Thier can be reached on (571) 272-2832. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENT KRUEGER/Primary Examiner, Art Unit 2474
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