CTNF 18/966,610 CTNF 78895 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2. This office action is in response to communication filed on 12/03/2024. Claims 1-20 are pending on this application. Double Patenting 08-30 AIA 3. A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co. , 151 U.S. 186 (1894); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert , 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. 08-31 AIA Claim s 3, 4, 16 and 20 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim s 1, 3, 14 and 18 of prior U.S. Patent No. 12,191,877, respectively . This is a statutory double patenting rejection. Double Patenting 08-33 AIA 4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-2 rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-2 of U.S. Patent No. 12,191,877; respectively . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-2 of U.S. Patent No. 12,191,877 disclose every limitation of applicant’s claims 1-2, respectively . 08-34 AIA Claim s 5-15 and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 4-14 and 15-17 of U.S. Patent No. 12,191,877, respectively . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 4-14 and 15-17 of U.S. Patent No. 12,191,877 disclose every limitation of applicant’s claims 5-15 and 17-19, respectively . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA 6. Claim s 1, 5, 6, 11 and 15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by MIYAHARA MASAYA ET AL: "22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers", IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, IEEE SERVICE CENTER, NEW YORK, NY, US, 9 February 2014 (2014-02-09), pages 388-389, XP032574937. (applicant’s Information Disclosure Statement (IDS)) . Regarding claim 1. Fig. 22.6.1 of MIYAHARA MASAYA ET AL. discloses An analog-to-digital converter circuit , comprising: a multi-bit input buffer (S/H) having a differential input (differential input of each S/H) coupled to receive a differential input sample (Vin), and configured to generate, at a plurality of differential outputs (differential output of each S/H), a plurality of residues (differential output of each S/H circuit is a residue of differential input sample signal Vin) the input sample (Vin) relative to a corresponding plurality of zero- crossing references (page 338, left Col. Discloses “ A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers ”); a plurality of zero-crossing comparators (plurality of V-T in Fig. 22.6.2) , each having a differential input (V INP /V INN inputs for each V-T in Fig. 22.6.2) coupled to receive one of the residues (V INP /V INN ) from one of the differential outputs of the input buffer (different output of each S/H) and having an output (output of each V-T) , each zero-crossing comparator (V-T) associated with a zone threshold (zone threshold of each V-T in Fig. 22.6.2) according to an ordered sequence of zone thresholds (order sequence of zone threshold of each V-T in Fig. 26.6.2) ; folding logic circuitry (Time-based Folder x 4) , having a plurality of inputs (input of Time-based Folder x 4), each coupled to the output of one of the comparators (V-T) , and configured to output a delay domain signal (D F1 …D F4 ) indicating a magnitude of the one of the residues (magnitude of residue output of each S/H) relative to a nearest zone threshold (nearest threshold of each V-T); and digital stage circuitry (Coarse SR latch, Fine Interpolated SAR Latch , Encoder) coupled to outputs of the zero-crossing comparators (V-T) and to outputs of the folding logic circuitry (Time-based Folder x 4), the digital stage circuitry (Coarse SR latch, Fine Interpolated SAR Latch , Encoder) configured to generate a digital output word (7-Bit) corresponding to the received input sample (Vin). Regarding claim 5. The circuit of claim 1, Fig. 22.6.1 further discloses wherein the digital stage circuitry (Coarse SR latch, Fine Interpolated SAR Latch , Encoder) comprises: a digital encoder (Encoder ) having inputs coupled to outputs of the comparators (output of each V-T) , and configured to encode one or more bits (bits of 15) of the digital output word (7 bit) to indicate an input range zone (range zone +V FS … - V FS ) of the input sample (Vin) between the zone thresholds (zone threshold of each V-T) associated with neighboring comparators (neighboring of each V-T) in the ordered sequence (order sequence of V INP /V INN for each V-T) having different polarities at their outputs (polarity output D P and D N of each V-T as discloses in Fig. 22.6.2) Regarding claim 6. The circuit of claim 1, Fig. 22.6.1 and Fig. 22.6.2 further discloses wherein the output of each of the comparators (V-T) comprise complementary single-ended outputs (complementary D P or D N of single end output of each V-T). Regarding claim 11. Fig. 22.6.1 of MIYAHARA MASAYA ET AL. discloses a method of converting an analog signal level (Vin) to a digital word (7 bit) , comprising the steps of: sampling (S/H) a differential input signal (Vin); generating, from the sampled input signal (Vin), a plurality of differential residue signals (differential residues signals outputs from each S/H) relative to a plurality of zero-crossing references (page 338, left Col. Discloses “ A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers ”); applying each differential residue signal differential residues signals outputs from each S/H) to a corresponding one of a plurality of zero-crossing comparators (V-T in Fig. 22.6.2) in an ordered sequence of zone thresholds (order sequence of zone threshold of each V-T) ; identifying an input range zone (+V FS ….-V FS ) for the sampled input signal (Vin) between the zone thresholds (zone thresholds of each V-T in Fig. 22.6.2) of neighboring comparators (neighboring of V-T in Fig. 22.6.2) in the ordered sequence (order sequence of each V-T) having a change in polarity at their outputs (change polarity of output DP/DN in Fig. 22.6.3); identifying a delay (D F1 …D F4 ) between logic transitions (DP/DN) at the neighboring comparators (neighboring of V-T); and encoding (Encoder) a digital output word (digital output 15) indicating the identified input range zone (+V FS ….-V FS ) and the identified delay (D F1 …D F4 ). Regarding claim 15. Fig. 22.6.1 of MIYAHARA MASAYA ET AL. discloses a voltage-to-delay conversion circuit, comprising: a multi-bit input buffer (S/H) having a differential input (differential input of S/H) coupled to receive a differential input sample (Vin) , and configured to generate, at a plurality of differential outputs (differential output of each S/H), a plurality of residues differential (output of each S/H circuit is a residue of differential input sample signal Vin) of the input sample (Vin) relative to a corresponding plurality of zero- crossing references (page 338, left Col. Discloses “ A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers ”); a plurality of zero-crossing comparators (plurality of V-T in Fig. 22.6.2), each having a differential input (V INP /V INN inputs for each V-T in Fig. 22.6.2) coupled to receive one of the residues V INP /V INN from one of the differential outputs of the input buffer (differential output of each S/H) and having an output (output of each V-T in Fig. 22.6.2), each zero-crossing comparator (each V-T) associated with a zone threshold (zone threshold of each V-T in Fig. 22.6.2) according to an ordered sequence of zone thresholds order sequence of zone threshold of each V-T in Fig. 26.6.2), so that the outputs of the zero-crossing comparators (output DP/DN of each V-T in Fig. 22.6.2) indicate an input range zone (range zone of +V FS ….-V FS ) of the input sample (Vin) between the zone thresholds (zone threshold of each V-T) associated with neighboring comparators (neighboring V-T) in the ordered sequence (order sequence of each V-T) having different polarities at their outputs (output polarities DP/DN of each V-T in F22.6.2) ; and folding logic circuitry (Time-based Folder x 4), having a plurality of inputs (inputs of (Time-based Folder x 4), each coupled to the output of one of the comparators (V-T), and configured to output a delay domain signal (D F1 …D F4 ) indicating a magnitude of the one of the residues (output of each S/H circuit is a residue of differential input sample signal Vin) relative to a nearest zone threshold (threshold zone of each V-T in Fig. 22.6.2). Allowable Subject Matter 7. Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the input stage comprises: first and second resistor ladders, each comprising a plurality of resistors connected in series; first and second transistors, the first transistor having a conduction path between a power supply node and the first resistor ladder, the second transistor having a conduction path between the first resistor ladder and a ground node, each of the first and second transistors having a control terminal coupled to a first input of the differential input; and third and fourth transistors, the third transistor having a conduction path between the power supply node and the second resistor ladder, the fourth transistor having a conduction path between the first resistor ladder and the ground node, each of the third and fourth transistors having a control terminal coupled to a second input of the differential input; wherein each the plurality of differential outputs comprises a node in the first resistor ladder and a corresponding opposing node in the second resistor ladder. 8. Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the folding logic circuitry comprises: a first plurality of logic functions, each having a first input coupled to a negative output of one of the comparators, a second input coupled to a positive output of another one of the comparators two places apart in the sequence from the one of the comparators, and an output; a first output logic function, having a plurality of inputs each coupled to an output of one of the first plurality of logic functions, and configured to present a logic transition at an output responsive to receiving a latest logic transition at its inputs; a second plurality of logic functions, each having a first input coupled to a negative output of one of the comparators, a second input coupled to a positive output of another one of the comparators two places apart in the sequence from the one of the comparators, and an output; a second output logic function, having a plurality of inputs each coupled to an output of one of the second plurality of logic functions, and configured to present a logic transition at an output responsive to receiving a latest logic transition at its inputs. 9. Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the step of generating the plurality of differential residue signals comprises: applying a first signal line from the sampled differential input signal to a first resistor ladder, the first resistor ladder having a first plurality of nodes among the resistors in the first resistor ladder, each of the first plurality of nodes coupled to a first input of a corresponding zero-crossing comparator; and applying a second signal line from the sampled differential input signal to a second resistor ladder, the second resistor ladder having a second plurality of nodes among the resistors in the second resistor ladder, each of the second plurality of nodes coupled to a second input of a corresponding zero-crossing comparator. 10. Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: chopping each of the differential residues at a frequency at or below one- half of a sampling frequency of the sampling step; wherein the applying step applies the chopped differential residues to inputs of the zero-crossing comparators. 11. Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the input stage comprises: first and second resistor ladders, each comprising a plurality of resistors connected in series; first and second transistors, the first transistor having a conduction path between a power supply node and the first resistor ladder, the second transistor having a conduction path between the first resistor ladder and a ground node, each of the first and second transistors having a control terminal coupled to a first input of the differential input; and third and fourth transistors, the third transistor having a conduction path between the power supply node and the second resistor ladder, the fourth transistor having a conduction path between the first resistor ladder and the ground node, each of the third and fourth transistors having a control terminal coupled to a second input of the differential input; wherein each the plurality of differential outputs comprises a node in the first resistor ladder and a corresponding opposing node in the second resistor ladder. 12. Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: a plurality of chopping stages, each coupled between an output of the input stage and the differential input of a corresponding comparator, and having an input coupled to receive a chop signal. 13. Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if filing a terminal disclaimer to overcome a non-statutory double patenting rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the output of each of the comparators comprise complementary single-ended outputs; and wherein the folding logic circuitry comprises: a first plurality of logic functions, each having a first input coupled to a negative output of one of the odd-numbered comparators in the sequence, a second input coupled to a positive output of another one of the odd-numbered comparators two places apart in the sequence from the one of the comparators, and an output; a first output logic function, having a plurality of inputs each coupled to an output of one of the first plurality of logic functions, and configured to present a logic transition at an output responsive to receiving a latest logic transition at its inputs; a second plurality of logic functions, each having a first input coupled to a negative output of an even-numbered one of the comparators, a second input coupled to a positive output of another one of the even-numbered comparators two places apart in the sequence from the one of the comparators, and an output; a second output logic function, having a plurality of inputs each coupled to an output of one of the second plurality of logic functions, and configured to present a logic transition at an output responsive to receiving a latest logic transition at its inputs. Contact Information 14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications. 05/07/2026 /LINH V NGUYEN/Primary Examiner, Art Unit 2845 Application/Control Number: 18/966,610 Page 2 Art Unit: 2845 Application/Control Number: 18/966,610 Page 3 Art Unit: 2845 Application/Control Number: 18/966,610 Page 4 Art Unit: 2845 Application/Control Number: 18/966,610 Page 5 Art Unit: 2845 Application/Control Number: 18/966,610 Page 6 Art Unit: 2845 Application/Control Number: 18/966,610 Page 7 Art Unit: 2845 Application/Control Number: 18/966,610 Page 8 Art Unit: 2845 Application/Control Number: 18/966,610 Page 9 Art Unit: 2845 Application/Control Number: 18/966,610 Page 10 Art Unit: 2845 Application/Control Number: 18/966,610 Page 11 Art Unit: 2845
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