DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/11/2026 have been fully considered but they are not persuasive.
Applicant argues on page 8 of the remarks that de Cesare does not disclose “responsive to authentication of the second request,…access to the region of memory” As can be seen in de Cesare col. 6, lines 42-58, teaches authentication to verify that the host computing device is authorized and then in turn sending encrypted memory key to memory controller 140 as further described in col. 6, lines 42-58. De Cesare further teaches memory controller performing mapping operations in col. 4, lines 62 – col. 5, line 5. Hence it, de Cesare teaches verifying authorization before memory mapping.
Applicant further argues that de Cesare does not teach “receive a first request from a first initiator to share a region of memory associated with a memory buffer device with a second initiator”. As can be seen in col. 6, lines 3-25, de Cesare describes device 101 as operating in a target disk mode whereby it allows other devices such as computing device 102 to access stored data after an authorization process. Going into a target disk mode is interpreted as a request to share memory.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by de Cesare, patent number: US 11 068 419.
As per claim 1, de Cesare teaches a memory buffer device comprising:
processing circuitry to receive a first request from a first initiator to share a region of memory associated with the memory buffer device with a second initiator (sending key to access memory to a hosting device, col. 9, line 66 – col. 10, line 62), wherein the processing circuitry is to:
identify a first passcode associated with the first initiator, wherein the first passcode is useable by at least the first initiator to access the region of memory (user key 331, col. 9, line 53-65);
receive a second request from the second initiator to access the region of memory, wherein the second request comprises a second passcode (receiving a request with a key, col. 10, lines 23 - 30);
authenticate the second request using the first passcode and the second passcode (verifying a key, col. 13, lines 6 - 24); and
responsive to authentication of the second request, generate a mapping between a host physical address space associated with the second initiator and a physical memory address space associated with the region of memory to enable the second initiator to access the region of memory (allowing access to specific region of memory after verification, col. 13, lines 25 - 50).
As per claim 2, de Cesare teaches wherein to identify the first passcode associated with the first initiator, the processing circuitry is to generate the first passcode based on an identifier associated with the first initiator (generating key, col. 10, lines 10-22).
As per claim 3, de Cesare teaches wherein to identify the first passcode associated with the first initiator, the processing circuitry is to receive the first passcode from the first initiator (comparing, col. 13, lines 6 - 24).
As per claim 4, de Cesare teaches wherein the first passcode is a public-private key pair (key, col 5, lines 26-52, col. 9, lines 65-col. 10, line 23).
As per claim 5, de Cesare teaches wherein the processing circuitry is further to:
receive a third request from the first initiator to revoke access associated with the second initiator to the region of the memory;
invalidate the first passcode; and
remove the mapping between the host physical address space associated with the second initiator and the physical memory address space associated with the region of memory associated with the memory buffer device (validity, col. 13, lines 6 - 24).
As per claim 6, de Cesare teaches wherein the processing circuitry is to include the mapping within an internal address translation table associated with the memory buffer device (memory controller, col. 12, lines 15 - 27).
As per claim 7, de Cesare teaches wherein the second initiator has read-only access to the region of memory (accessing memory, col. 13, lines 25 - 50).
As per claim 8, de Cesare teaches a memory module comprising:
a plurality of memory devices (memory 350, col. 12, lines 15 - 28); and
a memory buffer device operatively coupled to the plurality of memory devices, wherein the memory buffer device is to:
receive a first request from a first initiator to share a region of memory associated with the memory buffer device with a second initiator (sending key to access memory to a hosting device, col. 9, line 66 – col. 10, line 62);
receive a second request from the second initiator to access the region of memory (receiving a request with a key, col. 10, lines 23 - 30);
authenticate the second request (verifying a key, col. 13, lines 6 - 24); and
responsive to authentication of the second request, generate a mapping between a host physical address space associated with the second initiator and a physical memory address space associated with the region of memory to enable the second initiator to access the region of memory (allowing access to specific region of memory after verification, col. 13, lines 25 - 50).
As per claim 9, de Cesare teaches wherein to authenticate the second request, the memory buffer device is to:
identify a first passcode associated with the first initiator; and
authenticate the second request using the first passcode and a second passcode, wherein the second request comprises the second passcode (comparing, col. 13, lines 6 - 24).
As per claim 10, de Cesare teaches wherein to identify the first passcode associated with the first initiator, the memory buffer device is to generate the first passcode based on an identifier associated with the first initiator (generating key based on UID, col. 9, lines 52-65).
As per claim 11, de Cesare teaches wherein to identify the first passcode associated with the first initiator, the memory buffer device is to receive the first passcode from the first initiator (comparing, col. 13, lines 6 - 24).
As per claim 12, de Cesare teaches wherein the first passcode is a public-private key pair (key, col 5, lines 26-52, col. 9, lines 65-col. 10, line 23).
As per claim 13, de Cesare teaches wherein the memory buffer device is further to:
receive a third request from the first initiator to revoke access associated with the second initiator to the region of the memory;
invalidate the first passcode; and
remove the mapping between the host physical address space associated with the second initiator and the physical memory address space associated with the region of memory associated with the memory buffer device (validity, col. 13, lines 6 - 24).
As per claim 14, de Cesare teaches wherein the memory buffer device is to include the mapping within an internal address translation table associated with the memory buffer device (memory controller, col. 12, lines 15 - 27).
As per claim 15, de Cesare teaches wherein the second initiator has read-only access to the region of memory (accessing memory, col. 13, lines 25 - 50).
As per claim 16, de Cesare teaches a method comprising:
receiving a first request from a first initiator to share a region of memory associated with a memory buffer device with a second initiator (sending key to access memory to a hosting device, col. 9, line 66 – col. 10, line 62);
identifying a first passcode associated with the first initiator, wherein the first passcode is useable by at least the first initiator to access the region of memory (user key 331, col. 9, line 53-65);
receiving a second request from the second initiator to access the region of memory, wherein the second request comprises a second passcode (receiving a request with a key, col. 10, lines 23 - 30);
authenticating the second request using the first passcode and the second passcode (verifying a key, col. 13, lines 6 - 24); and
responsive to authenticating the second request, generating a mapping between a host physical address space associated with the second initiator and a physical memory address space associated with the region of memory to enable the second initiator to access the region of memory (allowing access to specific region of memory after verification, col. 13, lines 25 - 50).
As per claim 17, de Cesare teaches wherein identifying the first passcode associated with the first initiator comprises generating the first passcode based on an identifier associated with the first initiator (generating key based on UID, col. 9, lines 52-65).
As per claim 18, de Cesare teaches wherein identifying the first passcode associated with the first initiator comprises receiving the first passcode from the first initiator (comparing, col. 13, lines 6 - 24).
As per claim 19, de Cesare teaches wherein the first passcode is a public-private key pair (key, col 5, lines 26-52, col. 9, lines 65-col. 10, line 23).
As per claim 20, de Cesare teaches further comprising:
receiving a third request from the first initiator to revoke access associated with the second initiator to the region of the memory;
invalidating the first passcode; and
removing the mapping between the host physical address space associated with the second initiator and the physical memory address space associated with the region of memory associated with the memory buffer device (validity, col. 13, lines 6 - 24).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/OLUGBENGA O IDOWU/Primary Examiner, Art Unit 2494
